Datasheet

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LTC2752

2752f

Typical applicaTion

FeaTures

applicaTions

DescripTion

Dual16-Bit

SoftSpan I

OUT

DACs

The LTC

2752 is a dual 16-bit multiplying serial-input,

current-output digital-to-analog converter. It operates from

a single 3V to 5V supply and is guaranteed monotonic

over temperature. The LTC2752A provides full 16-bit

performance (±1LSB INL and DNL, max) over temperature

without any adjustments. This SoftSpan™ DAC offers

six output ranges (up to ±10V) that can be programmed

through the 3-wire SPI serial interface, or pinstrapped for

operation in a single range.

Any on-chip register (including DAC output-range set-

tings) can be read for veriﬁcation in just one instruction

cycle; and if you change register content, the altered

instruction cycle.

Voltage-controlled offset and gain adjustments are also

provided; and the power-on reset circuit and CLR pin both

reset the DAC outputs to 0V regardless of output range.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 5481178.

Dual 16-Bit V

OUT

DAC with Software-Selectable Ranges

Program or Pin-Strap Six Output Ranges

0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V

Maximum 16-Bit INL Error: ±1 LSB over

Temperature

Guaranteed Monotonic over Temperature

Glitch Impulse 0.6nV•s (3V), 2.2nV•s (5V)

Serial Readback of All On-Chip Registers

1μA Maximum Supply Current

2.7V to 5.5V Single-Supply Operation

16-Bit Settling Time: 2µs

Voltage-Controlled Offset and Gain Trims

Clear and Power-On-Reset to 0V Regardless of

Output Range

48-Pin 7mm × 7mm LQFP Package

High Resolution Offset and Gain Adjustment

Process Control and Industrial Automation

Automatic Test Equipment

Data Acquisition Systems

LTC2752

GND

ADJB

SPI with READBACK

–

DAC B

REFERENCE

OUTB

INA

REFA

REFERENCE

REFB

OFSA

OFSB

COMB

COMA

INB

OSADJB

ALL AMPLIFIERS 1/2 LT1469

OUT1B

OUT2B

FBB

ADJA

–

2752 TA01

OUTA

OSADJA

OUT1A

OUT2A

FBA

–

DAC A

CODE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

1.0

0.4

16384

32768

2752 TA01b

–0.6

0.6

0.8

0.2

49152

65535

±10V RANGE

Integral Nonlinearity (INL)

Summary of content (24 pages)

PAGE 1
LTC2752 Dual16-Bit SoftSpan IOUT DACs Features n n n n n n n n n n n Description Program or Pin-Strap Six Output Ranges 0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V Maximum 16-Bit INL Error: ±1 LSB over Temperature Guaranteed Monotonic over Temperature Glitch Impulse 0.6nV•s (3V), 2.2nV•s (5V) Serial Readback of All On-Chip Registers 1μA Maximum Supply Current 2.7V to 5.
PAGE 2
LTC2752 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) 48 47 46 45 44 43 42 41 40 39 38 37 ROFSA ROFSA RFBA RFBA IOUT1A VOSADJA VOSADJB IOUT1B RFBB RFBB ROFSB ROFSB TOP VIEW REFA 1 REFA 2 RCOMA 3 GEADJA 4 RINA 5 RINA 6 GND 7 IOUT2AS 8 IOUT2AF 9 GND 10 CS/LD 11 SDI 12 36 35 34 33 32 31 30 29 28 27 26 25 REFB REFB RCOMB GEADJB RINB RINB GND IOUT2BS IOUT2BF GND LDAC S2 SCK 13 SRO 14 GND 15 VDD 16 GND 17 GND 18 CLR 19 RFLAG 20 DNC 21 M-SPAN 22 S0 23 S1 24 IOUT1X , IOUT2X to GND...............
PAGE 3
LTC2752 Electrical Characteristics VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN LTC2752B TYP MAX MIN LTC2752A TYP MAX UNITS Static Performance Resolution l 16 16 Bits Monotonicity l 16 16 Bits DNL Differential Nonlinearity l ±1 ±0.2 ±1 LSB INL Integral Nonlinearity l ±2 ±0.
PAGE 4
LTC2752 Electrical Characteristics VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VDD Supply Voltage IDD VDD Supply Current Digital Inputs = 0V or VDD l VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V 2.7V ≤ VDD < 3.3V l l VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V 2.7V ≤ VDD ≤ 4.
PAGE 5
LTC2752 timing Characteristics otherwise specifications are at TA = 25°C.
PAGE 6
LTC2752 Typical Performance Characteristics VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted. 1.0 ±10V RANGE 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.2 0 –0.2 INL (LSB) 0.6 0.4 DNL (LSB) INL (LSB) 1.0 ±10V RANGE 0.8 INL vs Temperature Differential Nonlinearity (DNL) Integral Nonlinearity (INL) 1.0 0 –0.2 ±10V RANGE +INL 0.0 –0.2 –0.4 –0.4 –0.4 –0.6 –0.6 –0.6 –INL –0.8 –0.8 –0.8 –1.0 –1.0 –1.
PAGE 7
LTC2752 Typical Performance Characteristics VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted. INL vs Reference Voltage 1.0 0.8 DNL vs Reference Voltage 1.0 ±5V RANGE 0.8 0.6 0.6 0.4 +INL 0.2 +INL 0.0 –0.2 –INL –INL –0.6 –0.8 –0.8 6 8 +DNL –DNL –DNL –1.0 –10 –8 –6 –4 –2 0 2 V(RIN) (V) 10 2752 G07 1.0 ±10V RANGE 0.8 0 ±10V RANGE –20 0.4 0.4 DNL (LSB) +INL 0.0 –0.2 –INL 0.0 –0.4 –0.6 –0.8 –0.8 4 VDD (V) 4.5 5 5.5 2752 G09 –INL –0.2 –0.6 3.5 +INL 0.2 –0.
PAGE 8
LTC2752 Typical Performance Characteristics VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted. Logic Threshold vs Supply Voltage Supply Current vs Logic Input Voltage CLR, LDAC, SDI, SCK, CS/LD TIED TOGETHER LOGIC THRESHOLD (V) SUPPLY CURRENT (mA) 4 3 2 VDD = 5V 1 2 100 1.75 10 1.5 SUPPLY CURRENT (mA) 5 Supply Current vs Clock Frequency RISING 1.25 FALLING 1 ALTERNATING ZERO AND FULL-SCALE 1 VDD = 5V 0.1 VDD = 3V 0.01 0.001 0.
PAGE 9
LTC2752 Pin Functions REFA (Pins 1, 2): Feedback Resistor for the DAC A Reference Inverting Amplifier, and Reference Input for DAC A. The 20k feedback resistor is connected internally from REFA to RCOMA. For normal operation tie this pin to the output of the DAC A reference inverting amplifier (see Typical Applications). Typically –5V; accepts up to ±15V. Pins 1 and 2 are internally shorted together. RCOMA (Pin 3): Virtual Ground Point for the DAC A Reference Amplifier Inverting Resistors.
PAGE 10
LTC2752 Pin Functions S2 (Pin 25): Span Bit 2 Input. In Manual Span mode (MSPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or VDD even if they are unused. LDAC (Pin 26): Asynchronous DAC Load Input. When LDAC is a logic low, all DACs are updated (CS/LD must be high). IOUT2BF, IOUT2BS (Pins 28, 29): DAC B Current Output Complement Force and Sense Pins. Tie to ground via a clean, low impedance path.
PAGE 11
LTC2752 Block Diagram 16 VDD 4 3 RINA (5, 6) 2.56M 20k GEADJA RCOMA 20k 20k 2.
PAGE 12
LTC2752 Timing Diagram t1 t2 t3 1 SCK 2 t6 t4 31 32 t8 SDI LSB t5 t7 CS/LD t11 LDAC t9 SRO Hi-Z LSB 2752 TD 2752f 12
PAGE 13
LTC2752 Operation Output Ranges The LTC2752 is a dual, current-output, serial-input precision multiplying DAC with selectable output ranges. Ranges can either be programmed in software for maximum flexibility—each of the DACs can be programmed to any one of six output ranges—or hardwired through pin-strapping. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used.
PAGE 14
LTC2752 Operation writing code or span. If a 32-bit input sequence is used, the first eight bits must be zeros, followed by the same sequence as for a 24-bit wide input. Figure 3 shows the input and readback sequences for both 24-bit and 32-bit operations. When CS/LD is low, the SRO pin (Serial Readback Output) is an active output.The readback data begins after the command (C3-C0) and address (A3-A0) words have been shifted into SDI.
PAGE 15
SDI (WRITE SPAN) (WRITE CODE) C2 C1 C2 C1 COMMAND WORD C3 COMMAND WORD C3 C0 C0 A3 A3 A1 A1 A0 A0 0 D15 MSB 0 D14 0 D13 0 D12 0 D11 0 D9 12 ZEROS 0 D10 Figure 2.
PAGE 16
READBACK SPAN 0 0 0 0 0 2 0 Hi-Z 0 1 3 SRO SRO READBACK CODE Hi-Z SRO 0 0 SRO SDI SCK CS/LD Hi-Z C2 0 0 0 0 0 0 0 8 ZEROS 0 4 5 0 0 0 6 0 READBACK SPAN Hi-Z READBACK CODE 0 C3 SDI 2 C1 3 0 0 0 7 0 0 4 0 0 8 0 0 C0 0 COMMAND WORD 1 SCK CS/LD 0 0 C3 A1 7 C2 10 0 0 C1 11 0 0 0 0 0 0 8 0 D15 D15 9 0 D14 D14 10 0 D13 D13 11 0 D12 D12 12 0 D11 D11 13 0 D10 D10 14 D8 16 12 0 0 0 D9 0 D8 A1 15 0 0
PAGE 17
LTC2752 Operation SDI WRITE CODE DAC A WRITE CODE DAC B WRITE SPAN DAC C WRITE SPAN DAC B UPDATE ALL DACs ... SRO ... READ CODE INPUT REGISTER DAC A READ CODE INPUT REGISTER DAC B READ SPAN INPUT REGISTER DAC A READ SPAN INPUT REGISTER DAC B READ CODE DAC REGISTER DAC A 2754 F04 Figure 4. Rolling Readback Table 1.
PAGE 18
LTC2752 Operation Examples 1. Using a 24-bit instruction, load DAC A with the unipolar range of 0V to 10V, output at zero volts and DAC B with the bipolar range of ±10V, outputs at zero volts. Note all DAC outputs should change at the same time.
PAGE 19
LTC2752 Operation The offset adjust pin VOSADJX can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range: ∆VOS [LSB] = – VVOSADJX • 512 VRINX A 5V control voltage applied to VOSADJX produces ∆VOS = –512 LSB in any output range, assuming a 5V reference voltage at RINX. In voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (These functions hold regardless of reference voltage.
PAGE 20
LTC2752 Applications Information Op Amp Selection of op amps to meet the system’s specified error budget. Select the amplifier from Table 6 and insert the specified op amp parameters in Table 5. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate.
PAGE 21
LTC2752 Applications Information Op amp offset will contribute mostly to output offset and gain error, and has minimal effect on INL and DNL. For example, for the LTC2752 with a 5V reference in 5V unipolar mode, a 250µV op amp offset will cause a 3.3LSB zeroscale error and a 3.3LSB gain error; but only 0.75LSB of INL degradation and 0.2LSB of DNL degradation.
PAGE 22
LTC2752 Applications Information in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. The best strategy here is to tie the pins to the star ground plane by multiple vias located directly underneath the part.
PAGE 23
LTC2752 Package Description LX Package 48-Lead Plastic LQFP (7mm × 7mm) (Reference LTC DWG # 05-08-1760 Rev Ø) 7.15 – 7.25 9.00 BSC 5.50 REF 7.00 BSC 48 0.50 BSC 1 2 48 SEE NOTE: 4 1 2 9.00 BSC 5.50 REF 7.00 BSC 7.15 – 7.25 0.20 – 0.30 A A PACKAGE OUTLINE C0.30 – 0.50 1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.60 1.35 – 1.45 MAX 11° – 13° R0.08 – 0.20 GAUGE PLANE 0.25 0° – 7° 11° – 13° 0.09 – 0.20 1.00 REF 0.50 BSC 0.17 – 0.27 0.05 – 0.
PAGE 24
LTC2752 Typical Application Digitally Controlled Offset and Gain Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply 3 2 15V 2 C6 10µF IN OUT LT1236-5 5V REFERENCE 6 C7 10µF 4 15V 7 16 450k CS2 SPI BUS SDI SCK 4 6 5 1 7 VCC REF VOUTA CS/LD VOUTB SDI VOUTC SCK VOUTD 10 2 LTC2634-MSELMX12 1 3 6 33 42 –15V 10 LT1991 1 4 43 4 9 10, 11 VDD 450k 8 GND – + 450k 15V LT1012A 7 6 4 C1 –15V 100pF C2 0.