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LTC2756

2756f

Typical applicaTion

FeaTures

applicaTions

DescripTion

Serial 18-Bit SoftSpan

OUT

DAC

The LTC

2756 is an 18-bit multiplying serial-input, cur-

rent-output digital-to-analog converter. LTC2756A provides

full 18-bit performance—INL and DNL of ±1LSB maxi-

mum—over temperature without any adjustments. 18-bit

monotonicity is guaranteed in all performance grades. This

SoftSpan™ DAC operates from a single 3V to 5V supply

and offers six output ranges (up to ±10V) that can be

programmed through the 3-wire SPI serial interface or

pin-strapped for operation in a single range.

Any on-chip register (including DAC output-range set-

tings) can be read for verification in just one instruction

cycle; and if you change register content, the altered

instruction cycle.

Voltage-controlled offset and gain adjustments are also

provided; and the power-on reset circuit and CLR pin both

reset the DAC output to 0V regardless of output range.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation and SoftSpan is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

18-Bit Voltage Output DAC with Software-Selectable Ranges

Maximum 18-Bit INL Error: ±1 LSB Over Temperature

Program or Pin-Strap

Six Output Ranges:

0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V

Guaranteed Monotonic Over Temperature

Glitch Impulse 0.4nV• s (3V), 2nV•s (5V)

18-Bit Settling Time: 2.1µs

2.7V to 5.5V Single Supply Operation

Reference Current Constant for All Codes

Voltage-Controlled Offset and Gain Trims

Serial Interface with Readback of All Registers

Clear and Power-On-Reset to 0V Regardless of

Output Range

28-Pin SSOP Package

Instrumentation

Medical Devices

Automatic Test Equipment

Process Control and Industrial Automation

LTC2756 Integral Nonlinearity

150pF

–

LT1012

–

LT1468

18-BIT DAC WITH SPAN SELECT

LTC2756

OSADJ

COM

OFS

REF

OUT1

OUT

OUT2

GND

GAIN

ADJUST

ADJ

27pF

0.1µF

2756 TA01a

SPI WITH

READBACK

OFFSET

ADJUST

CODE

0 65536

–1.0

INL (LSB)

–0.8

–0.6

–0.4

–0.2

0.6

0.4

0.2

0.8

1.0

131072 196608 262143

2756 TA01b

0V TO 10V RANGE

Summary of content (24 pages)

PAGE 1
LTC2756 Serial 18-Bit SoftSpan IOUT DAC Features n n n n n n n n n n n Description Maximum 18-Bit INL Error: ±1 LSB Over Temperature Program or Pin-Strap Six Output Ranges: 0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V Guaranteed Monotonic Over Temperature Glitch Impulse 0.4nV • s (3V), 2nV • s (5V) 18-Bit Settling Time: 2.1µs 2.7V to 5.
PAGE 2
LTC2756 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) TOP VIEW IOUT1, IOUT2 to GND................................................±0.3V RIN, RCOM, REF, RFB, ROFS, VOSADJ, GEADJ to GND.......................................................... ±18V VDD to GND................................................... –0.3V to 7V Digital Inputs to GND.................................... –0.3V to 7V Digital Outputs to GND ..... –0.3V to VDD +0.3V (Max 7V) Operating Temperature Range LTC2756C...............
PAGE 3
LTC2756 Electrical Characteristics VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN LTC2756B TYP MAX MIN LTC2756A TYP MAX UNITS Static Performance Resolution l 18 18 18 Bits 18 Bits Monotonicity l DNL Differential Nonlinearity l ±1 ±0.25 ±1 LSB INL Integral Nonlinearity l ±2 ±0.
PAGE 4
LTC2756 Electrical Characteristics VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VDD Supply Voltage IDD Supply Current, VDD Digital Inputs = 0V or VDD l VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V 2.7V ≤ VDD < 3.3V l l VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V 2.7V ≤ VDD ≤ 4.
PAGE 5
LTC2756 timing Characteristics otherwise specifications are at TA = 25°C.
PAGE 6
LTC2756 Typical Performance Characteristics VDD = 5V, V(RIN) = 5V, TA = 25°C, unless otherwise noted. Integral Nonlinearity (INL) 1.0 0V TO 10V RANGE 0.8 0.8 0.6 0.6 0.4 0.4 0.4 0.2 0.2 0.2 0 –0.2 INL (LSB) 0.6 0 –0.2 0 –0.2 –0.4 –0.4 –0.4 –0.6 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 –1.0 65536 131072 CODE 196608 262143 0 65536 131072 CODE 196608 2756 G02 INL vs Temperature 0.8 DNL vs Temperature 1.0 0V TO 10V RANGE 0.6 0.8 DNL (LSB) 0 –INL 0 –0.6 –0.6 –0.8 –0.
PAGE 7
LTC2756 Typical Performance Characteristics VDD = 5V, V(RIN) = 5V, TA = 25°C, unless otherwise noted. INL vs VDD 1.0 1.0 0V TO 10V RANGE 0.8 0.8 0.6 0 0V TO 10V RANGE –20 0.6 +INL 0.4 DNL (LSB) 0.2 0 –INL –0.2 0.2 +DNL 0 –0.2 –DNL –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 2.5 –1.0 2.5 3 3.5 4 4.5 VDD (V) 5 5.5 ATTENUATION (dB) 0.
PAGE 8
LTC2756 Pin Functions ROFS (Pin 1): Bipolar Offset Resistor. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at RIN (Pin 5). REF (Pin 2): DAC Reference Input, and Feedback Resistor for the Reference Inverting Amplifier. The external reference inverting amplifier sees as its load the 10k DAC reference input resistance in parallel with the 20k feedback resistor.
PAGE 9
LTC2756 Pin Functions S0 (Pin 20): Span Bit 0 Input. In Manual Span mode (M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range. These pins must be tied to either GND or VDD even if they are unused. S1 (Pin 21): Span Bit 1 Input. In Manual Span mode (M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range. These pins must be tied to either GND or VDD even if they are unused. S2 (Pin 22): Span Bit 2 Input.
PAGE 10
LTC2756 Block Diagram 4 GEADJ 3 RCOM 2 1 REF RFB 27, 28 ROFS 2.
PAGE 11
LTC2756 Timing Diagram t1 t2 t3 1 SCK 2 t6 t4 31 32 t8 SDI LSB t5 t7 CS/LD t11 LDAC t9 SRO Hi-Z LSB 2756 TD 2756f 11
PAGE 12
LTC2756 Operation Output Ranges Input and DAC Registers The LTC2756 is a current-output, serial-input precision multiplying DAC with selectable output ranges. Ranges can either be programmed in software for maximum flexibility—the DAC can be programmed to any one of six output ranges—or hardwired through pin-strapping. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V).
PAGE 13
LTC2756 Operation Serial Interface When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock (SCK pin). The loading sequence required for the LTC2756 is one byte consisting of a 4-bit command word (C3 C2 C1 C0) and four zeros, then three bytes (24 bits) of data. When writing a code, the code data is left (MSB) justified; so that the 24-bit data field consists of 18 code bits followed by 6 don’t-care bits.
PAGE 14
LTC2756 Operation Table 1.
PAGE 15
SRO SRO SDI C3 SDI 0 0 C1 3 C1 0 0 0 0 COMMAND C2 READBACK SPAN Hi-Z 2 COMMAND C2 READBACK CODE Hi-Z WRITE SPAN C3 WRITE CODE 1 SCK CS/LD 0 0 C0 C0 4 0 0 0 0 5 0 0 0 0 0 0 4 ZEROS 0 4 ZEROS 0 6 7 0 0 0 0 8 0 D17 X D17 9 0 D16 X D16 10 0 0 D14 X D14 12 0 D13 X D13 X D12 14 X D11 15 0 D12 0 D11 12 DON’T-CARE 13 0 D10 X D10 D9 17 D8 18 0 D9 X 0 D8 X 19 0 D7 X D7 18-BIT DAC CODE 16 0 D6 X D6 20 S3 D5
PAGE 16
LTC2756 Operation SDI WRITE CODE WRITE SPAN UPDATE WRITE CODE ... SRO ... READ CODE INPUT REGISTER READ SPAN INPUT REGISTER READ SPAN DAC REGISTER READ CODE INPUT REGISTER 2756 F03 Figure 3.
PAGE 17
LTC2756 operation Examples 1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output stays at 0V throughout the example. 3. Write and update mid-scale code in 0V to 10V range (VOUT = 5V) using readback to check the contents of the Input registers before updating. a) CS/LD ↓. Clock SDI: 00100000 XXXXXXXX XXXX0010 XXXXXXXX a) CS/LD ↓. Clock SDI: 00110000 10000000 00000000 00XXXXXX b) CS/LD ↑ Span Input register – range set to bipolar ±5V.
PAGE 18
LTC2756 operation System Offset and Reference Adjustments Many systems require compensation for overall system offset. This may be an order of magnitude or more greater than the offset of the LTC2756, which is so low as to be dominated by external output amplifier errors even when using the most precise op amps. The offset adjust pin VOSADJ can be used to null unipolar offset or bipolar zero error.
PAGE 19
LTC2756 Applications Information Op Amp Selection Because of the extremely high accuracy of the 18-bit LTC2756, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Table 3. Coefficients for the Equations of Table 4 OUTPUT RANGE A1 A2 A3 A4 A5 5V 1.1 2 1 – 1 10V 2.2 3 0.5 – 1.
PAGE 20
LTC2756 Applications Information Op amp offset contributes mostly to DAC output offset and gain error, and has minimal effect on INL and DNL. For example, consider the LTC2756 in unipolar 5V output range. (Note that for this example, the LSB size is 19µV.) An op amp offset of 35µV will cause 1.8LSB of output offset, and 1.8LSB of gain error; but 0.4LSB of INL, and just 0.1LSB of DNL.
PAGE 21
LTC2756 Applications Information Table 6. Partial List of LTC Precision References Recommended for Use with the LTC2756 with Relevant Specifications INITIAL TOLERANCE TEMPERATURE DRIFT 0.1Hz to 10Hz NOISE LT1019A-5, LT1019A-10 ±0.05% max 5ppm/°C max 12µVP-P LT1236A-5, LT1236A-10 ±0.05% max 5ppm/°C max 3µVP-P LT1460A-5, LT1460A-10 ±0.075% max 10ppm/°C max 20µVP-P LT1790A-2.5 ±0.05% max 10ppm/°C max 12µVP-P LTC6652A-5 ±0.05% max 5ppm/°C max 2.8ppmP-P LTC6655A-2.5 LTC6655A-5 ±0.
PAGE 22
LTC2756 Applications Information CIRCUIT B CIRCUIT A + 2 1000pF LT1468 ZETEX BAT54S 7 6 IOUT2 3 LT1012 + 1 – 6 IOUT2 2 – 7 200Ω 200Ω 1 2 3 ZETEX* BAT54S 3 2 3 *SCHOTTKY BARRIER DIODE VREF 5V 1 ROFS RFB 27, 28 5 RIN + 6 3 4 LT1012 GEADJ 3 RCOM 2 27pF DAC IOUT1 26 2 – IOUT2 7 3 + LT1468 6 VOUTA VOSADJ 25 – 150pF 2 REF LTC2756 2756 F05 Figure 4. If a Low-Impedance GND Plane Is Unavailable, Drive IOUT2 with a Force/Sense Amplifier As Shown.
PAGE 23
LTC2756 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 9.90 – 10.50* (.390 – .413) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1.25 ±0.12 7.8 – 8.2 5.3 – 5.7 0.42 ±0.03 7.40 – 8.20 (.291 – .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RECOMMENDED SOLDER PAD LAYOUT 2.0 (.079) MAX 5.00 – 5.60** (.197 – .221) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.55 – 0.
PAGE 24
LTC2756 Typical Application 15V 12V IN + OUT LT6655-5 LT1012 0.1µF 10µF – –15V 1 14 10k 23 10k 17 25 4 19 20 21 22 VDD ROFS 5 3 RIN RCOM 100pF 2 REF RFB LDAC IOUT1 27, 28 26 LTC2756 CLR VOUT 1k 10k VOSADJ 10k GEADJ 1µF M-SPAN S0 S2 9 SDI SCK 10 SRO 11 + IOUT2 7 6, 8, 13, 15, 16, 24 GND S1 CS/LD – – 5V LTC2054 –5V 1k + 10Ω 5V 100pF 15V LTC6240 + –5V – LTC1360 5pF 1µF –15V 2756 TA02 12 4.02k 1k SPI BUS Figure 5.