Datasheet

LTC2862/LTC2863/
LTC2864/LTC2865
14
2862345fc
For more information www.linear.com/LTC2862
Hi-Z State
The receiver output is internally driven high (to V
CC
or V
L
)
or low (to GND) with no external pull-up needed. When the
receiver is disabled the RO pin becomes Hi-Z with leakage
of less than ±5μA for voltages within the supply range.
High Receiver Input Resistance
The receiver input load from A or B to GND for the LTC2863,
LTC2864, and LTC2865 is less than one-eighth unit load,
permitting a total of 256 receivers per system without
exceeding the RS485 receiver loading specification. All
grades of the LTC2862 and the H- and MP-grade devices
of the LTC2863, LTC2864, and LTC2865 have an input
load less than one-seventh unit load over the complete
temperature range of –40°C to 125°C. The increased input
load specification for these devices is due to increased
junction leakage at high temperature and the transmitter
circuitry sharing the A and B pins on the LTC2862. The
input load of the receiver is unaffected by enabling/disabling
the receiver or by powering/unpowering the part.
Supply Current
The unloaded static supply currents in these devices
are low —typically 900μA for non slew limited devices
and 3.3mA for
slew limited devices. In applications
with resistively terminated cables, the supply current is
dominated by the driver load. For example, when using two
120Ω terminators with a differential driver output voltage
of 2V, the DC load current is 33mA, which is sourced by
the positive voltage supply. Power supply current increases
with toggling data due to capacitive loading and this term
can increase significantly at high data rates. A plot of
the supply current vs data rate is shown in the Typical
Performance Characteristics of this data sheet.
During fault conditions with a positive voltage larger than
the supply voltage applied to the transmitter pins, or during
transmitter operation with a high positive common mode
voltage, positive current of up to 80mA may flow from the
transmitter pins back to V
CC
. If the system power supply
or loading cannot sink this excess current, a 5.6V 1W
1N4734 Zener diode may be placed between V
CC
and GND
to prevent an overvoltage condition on V
CC
.
There are no power-up sequence restrictions on the
LTC2865. However, correct operation is not guaranteed for
V
L
> V
CC
.
Shutdown Mode Delay
The LTC2862, LTC2864, and LTC2865 feature a low power
shutdown
mode that is entered when both the driver and
the receiver are simultaneously disabled (pin DE low and
RE high). A shutdown mode delay of approximately 250ns
(not tested in production) is imposed after this state is
received before the chip enters shutdown. If either DE goes
high or RE goes low during this delay, the delay timer is
reset and the chip does not enter shutdown. This reduces
the chance of accidentally entering shutdown if DE and
RE are driven in parallel by a slowly changing signal or if
DE and RE are driven by two independent signals with a
timing skew between them.
This shutdown mode delay does not affect the outputs of
the transmitter and receiver, which start to switch to the
high impedance state upon the reception of their respec-
tive disable signals as defined by the parameters t
SHDND
and t
SHDNR
. The shutdown mode delay affects only the
time when all the internal circuits that draw DC power
from V
CC
are turned off.
High Speed Considerations
A ground plane layout with a 0.1µF bypass capacitor placed
less than 7mm away from the V
CC
pin is recommended. The
PC board traces connected to signals A/B and Z/Y should
be
symmetrical and as short as possible to maintain good
differential signal integrity. To minimize capacitive effects,
the differential signals should be separated by more than
the width of a trace and should not be routed on top of
each other if they are on different signal planes.
Care should be taken to route outputs away from any
sensitive inputs to reduce feedback effects that might
cause noise, jitter, or even oscillations. For example, in
the full-duplex devices, DI and A/B should not be routed
near the driver or receiver outputs.
The logic inputs have a typical hysteresis of 100mV to
provide noise immunity. Fast edges on the outputs can
cause glitches in the ground and power supplies which are
applicaTions inForMaTion