Datasheet

LTC2870/LTC2871
26
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applicaTions inForMaTion
Layout Considerations
All V
CC
pins must be connected together on the PC board
with very low impedance traces or with a dedicated plane.
A 2.2µF or larger decoupling capacitor (C4 in Figure13)
must be placed less than 0.7cm away from the V
CC
pin
that is adjacent to the V
DD
pin.
0.1µF capacitors to GND can be added on the V
CC
pins
adjacent to the B and V
L
pins if the connection to the 2.2µF
decoupling capacitor is not direct or if the trace is very
narrow. All GND pins must be connected together and
all V
EE
pins must be connected together, including the
exposed pad on the bottom of the package. The bypass
capacitor at V
EE
, C3, should be positioned closest to the
V
EE
pin that is adjacent to the CAP pin, with no more than
1cm of total trace length between the V
EE
and GND pins.
Place the charge pump capacitor, C1, directly adjacent to
the SW and CAP pins, with no more than one centimeter
of total trace length to maintain low inductance. Close
placement of the inductor, L1, is of secondary importance
compared to the placement of C1 but should include no
more than two centimeters of total trace length. Figure14,
shows an excellent example of a layout for these external
components on the bottom of the LTC2871 Demo Circuit
1786A.
The PC board traces connected to high speed signals A/B
and Y/Z should be symmetrical and as short as possible
to minimize capacitive imbalance and maintain good dif
-
ferential signal integrity. To minimize capacitive loading
effects, the differential signals should be separated by
more than the width of a trace.
Route outputs away from sensitive inputs to reduce feed-
back effects that might cause noise, jitter, or even oscilla-
tions. For example, do not route DI or A/B near the driver
or receiver outputs.
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