Datasheet

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LTC3718

3718fa

FEATURES

APPLICATIO S

DESCRIPTIO

TYPICAL APPLICATIO

Low Input Voltage

DC/DC Controller for

DDR/QDR Memory Termination

■

Very Low V

IN(MIN)

: 1.5V

■

Ultrafast Transient Response

■

True Current Mode Control

■

5V Drive for N-Channel MOSFETs Eliminates

Auxillary 5V Supply

■

No Sense Resistor Required

■

Uses Standard 5V Logic-Level N-Channel MOSFETs

■

OUT(MIN)

: 0.4V

■

OUT

Tracks 1/2 V

or External V

REF

■

Symmetrical Source and Sink Output Current Limit

■

Adjustable Switching Frequency

■

ON(MIN)

<100ns

■

Power Good Output Voltage Monitor

■

Programmable Soft-Start

■

Output Overvoltage Protection

■

Optional Short-Circuit Shutdown Timer

■

Small 24-Lead SSOP Package

■

Bus Termination: DDR/QDR Memory, SSTL, HSTL, ...

■

Servers, RAID Systems

■

Distributed Power Systems

■

Synchronous Buck with General Purpose Boost

The LTC

3718 is a high current, high efficiency synchro-

nous switching regulator controller for DDR and QDR

memory termination. It operates from an input as low as

1.5V and provides a regulated output voltage equal to

(0.5)V

. The controller uses a valley current control

architecture to enable high frequency operation with very

low on-times without requiring a sense resistor. Operating

frequency is selected by an external resistor and is com-

pensated for variations in V

and V

OUT

. The LTC3718 uses

a pair of standard 5V logic level N-channel external

MOSFETs, eliminating the need for expensive P-channel

or low threshold devices.

Forced continuous operation reduces noise and RF inter-

ference. Fault protection is provided by internal foldback

current limiting, an output overvoltage comparator and an

optional short-circuit timer. Soft-start capability for sup-

ply sequencing can be accomplished using an external

timing capacitor. OPTI-LOOP

compensation allows the

transient response to be optimized over a wide range of

loads and output capacitors.

Efficiency vs Load Current

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a registered trademark of Linear Technology Corporation. No R

SENSE

is a

trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a

new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc.

0.1µF

4.75k

LTC3718

C1 820pF X7R

237k

12.1k

OUT

: SANYO POSCAP 4TPB470M L1: SUMIDA CEP125-0R8MC L2: PANASONIC ELJPC4R7MF

37.4k

IN2

4.7µF

4.7µH

Si7440DP

B340A

3718 TA01

L1 0.8µH

MBR0520

VCC1

10µF

0.33µF

CMDSH-3

OUT

470µF

×2

Si7440DP

2.5V

OUT

1.25V

±10A

IN1

22µF

×2

B340A

SHDN BOOST

REF

SW1

FB1

SENSE

PGOOD PGND1

RUN/SS

SENSE

–

SGND1

INTV

SGND2

IN1

FB2

SW2

PGND2

IN2

OUT

Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.01 1 10 100

3718 G05/TA01a

0.1

= 2.5V

OUT

= 1.25V

FIGURE 1 CIRCUIT

Summary of content (20 pages)

PAGE 1
LTC3718 Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®3718 is a high current, high efficiency synchronous switching regulator controller for DDR and QDRTM memory termination. It operates from an input as low as 1.5V and provides a regulated output voltage equal to (0.5)VIN. The controller uses a valley current control architecture to enable high frequency operation with very low on-times without requiring a sense resistor.
PAGE 2
LTC3718 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN2) .......................10V to – 0.3V Boosted Topside Driver Supply Voltage (BOOST) ............................................... 42V to – 0.3V VIN1, ION, SW1 Voltage ............................. 36V to – 0.3V RUN/SS, PGOOD Voltages ......................... 7V to – 0.3V VON, VREF, VRNG Voltages .......(INTVCC + 0.3V) to – 0.3V ITH, VFB1 Voltages .................................... 2.
PAGE 3
LTC3718 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN1 = 15V, VIN2 = 1.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VRUN/SS(LT) RUN Pin Latchoff Threshold RUN/SS Pin Falling IRUN/SS(C) Soft-Start Charge Current VRUN/SS = 0V IRUN/SS(D) Soft-Start Discharge Current VRUN/SS = 4.
PAGE 4
LTC3718 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3718EG: TJ = TA + (PD • 130°C/W) Note 3: The LTC3718 is tested in a feedback loop that adjusts VFB1 to achieve a specified error amplifier output voltage (ITH). Note 4: The LTC3718 is guaranteed to meet performance specifications from 0°C to 70°C.
PAGE 5
LTC3718 U W TYPICAL PERFOR A CE CHARACTERISTICS Frequency vs Input Voltage Load Regulation 450 0 400 LOAD = 10A VIN = 2.5V VOUT = 1.25V –0.1 300 250 ∆VOUT/VOUT (%) FREQUENCY (kHz) 350 LOAD = 0A 200 150 –0.2 –0.3 –0.4 100 –0.5 VOUT = 1.25V FIGURE 1 CIRCUIT 50 FIGURE 1 CIRCUIT –0.6 0 1.5 1.7 1.9 2.1 2.3 2.5 INPUT VOLTAGE (V) 2.7 2.9 1 0 2 3 4 5 6 7 LOAD CURRENT (A) 3718 G07 VOUT 1V/DIV IL 5A/DIV IL 2A/DIV VIN = 2.5V 20µs/DIV VOUT = 1.
PAGE 6
LTC3718 U W TYPICAL PERFOR A CE CHARACTERISTICS –0.1 2 –0.2 –0.3 5.0 RUN/SS THRESHOLD (V) 3 FCB PIN CURRENT (µA) ∆INTVCC (%) 0 PULL-DOWN CURRENT 1 0 PULL-UP CURRENT LATCHOFF ENABLE 4.0 3.5 0 10 30 40 20 INTVCC LOAD CURRENT (mA) LATCHOFF THRESHOLD –2 –50 –25 50 50 25 0 75 TEMPERATURE (°C) 100 Undervoltage Lockout Threshold vs Temperature 3.0 2.5 75 0 25 50 TEMPERATURE (C) 100 125 300 250 200 150 100 50 0 0.50 0.75 1.00 1.25 1.50 VRNG (V) 1.75 3718 G17 2.
PAGE 7
LTC3718 U U U PI FU CTIO S RUN/SS (Pin 1): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/µF) and the time delay for overcurrent latchoff (see Applications Information). Forcing this pin below 0.8V shuts down the device. VON (Pin 2): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT. The comparator input defaults to 0.
PAGE 8
LTC3718 W FU CTIO AL DIAGRA S U U RON VIN VON 2 16 VIN1 7 ION + CIN 0.7V 2.4V 0.8V REF 5V REG BOOST tON = 24 VVON (10pF) IION R S Q SW1 22 + ICMP SENSE+ SWITCH LOGIC IREV L1 21 – – M1 23 ON 20k + CB TG VOUT DB INTVCC 17 SHDN 1.4V + OV COUT CVCC BG M2 18 VRNG PGND1 4 × 19 SENSE – 20 0.7V PGOOD 3 5.7µA 1 240k + Q2 3/10VREF UV – ITHB R3 20k VFB1 8 Q1 R4 40k + Q5 SGND1 OV 6 – – SS RUN SHDN + 1.2µA EA + – – + VREF 9 11/30VREF 6V 0.
PAGE 9
LTC3718 U OPERATIO Main Control Loop INTVCC Power The LTC3718 is a current mode controller for DC/DC step-down converters designed to operate from low input voltages. It incorporates a boost converter with a buck regulator. Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the INTVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB.
PAGE 10
LTC3718 U W U U APPLICATIO S I FOR ATIO A typical LTC3718 application circuit is shown in Figure 1. External component selection is primarily determined by the maximum load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC3718 uses the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value.
PAGE 11
LTC3718 U W U U APPLICATIO S I FOR ATIO ρT NORMALIZED ON-RESISTANCE 2.0 tON = 1.5 Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: 1.0 0.5 f= 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3718 F02 Figure 2.
PAGE 12
LTC3718 U W U U APPLICATIO S I FOR ATIO RVON1 30k RVON1 3k VON VOUT CVON 0.01µF RVON2 100k LTC3718 RC ITH VOUT 10k CVON 0.01µF RVON2 10k INTVCC VON LTC3718 RC Q1 2N5087 ITH CC CC (3a) 3718 F03 (3b) Figure 3. Adjusting Frequency Shift with Load Current Changes filter out the ITH variations at the switching frequency. The resistor load on ITH reduces the DC gain of the error amp and degrades load regulation, which can be avoided by using the PNP emitter follower of Figure 3b.
PAGE 13
LTC3718 U W U U APPLICATIO S I FOR ATIO transients. The output ripple ∆VOUT is approximately bounded by:  1  ∆VOUT ≤ ∆IL  ESR +  8fC OUT   Since ∆IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements.
PAGE 14
LTC3718 U W U U APPLICATIO S I FOR ATIO due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON Soft-Start and Latchoff with the RUN/SS Pin Output Voltage Programming When VFB is connected to VOUT, the output voltage is regulated to one half of the voltage at the VREF pin.
PAGE 15
LTC3718 U W U U APPLICATIO S I FOR ATIO persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 4V threshold.
PAGE 16
LTC3718 U W U U APPLICATIO S I FOR ATIO 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss.
PAGE 17
LTC3718 U W U U APPLICATIO S I FOR ATIO ESR of 0.005Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: and double check the assumed TJ in the MOSFET: 2 PBOT 2.5V – 1.25V  9.9A  =   (1.15)(0.013Ω) 2.5V  2  ∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (2.6A) (0.005Ω) = 13mV = 0.18W However, a 0A to 6A load step will cause an output change of up to: TJ = 50°C + (0.
PAGE 18
LTC3718 U W U U APPLICATIO S I FOR ATIO PC Board Layout Checklist • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer.
PAGE 19
LTC3718 U TYPICAL APPLICATIO One Half VIN, ±10A Bus Terminator CSS 0.1µF X7R RPG 100k 1 2 3 PGOOD C1 820pF X7R 4 RC 4.75k 5 C2 100pF 6 RON 237k 7 8 9 10 11 12 RUN/SS VON TG PGOOD SW1 21 ITH SENSE – 20 PGND1 LTC3718 ION BG VFB1 INTVCC VREF VIN1 SHDN VIN2 PGND2 SGND2 SW2 VFB2 M1 Si7440DP CIN2**** 330µF D1 B340A 22 SENSE + SGND1 CB 0.33µF X7R 23 VRNG RF3 10k RF1 12.1k BOOST DB CMDSH-3 24 VIN 2.5V CIN1 22µF X5R ×2 L1** 0.
PAGE 20
LTC3718 U TYPICAL APPLICATIO Dual Output 2.5V, ±10A Buck Converter and 5V to 12V/130mA Boost Converter CSS 0.1µF X7R RPG 100k 1 2 3 PGOOD C1 3300pF X7R 4 RC 10k 5 C2 100pF RON 237k 6 7 RFB 249k 8 RREF 499k 9 10 11 12 RF3 10k RF1 12.3k RUN/SS BOOST VON TG SW1 PGOOD SENSE + VRNG ITH SENSE SGND1 – PGND1 LTC3718 ION BG VFB1 INTVCC VREF VIN1 SHDN VIN2 SGND2 PGND2 VFB2 SW2 VIN 6V TO 24V CIN1**** 33µF ×2 25V DB CMDSH-3 24 CB 0.