Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsPMICsPMIC - voltage regulators - DC DC switch controllers PolyPhase® SSOP 24

LTC3736-1

37361f

Dual 2-Phase, No R

SENSE

Synchronous Controller with

Spread Spectrum

Low Noise, 2-Phase, Dual Synchronous DC/DC Step-Down Converter

■

Spread Spectrum Operation

■

Tracking Function

■

No Current Sense Resistors Required

■

Out-of-Phase Controllers Reduce Required

Input Capacitance

■

Wide V

Range: 2.75V to 9.8V

■

Current Mode Operation

■

0.6V ±1.5% Voltage Reference

■

Low Dropout Operation: 100% Duty Cycle

■

Pulse Skipping Operation at Light Loads

■

Internal Soft-Start Circuitry

■

Power Good Output Voltage Monitor

■

Output Overvoltage Protection

■

Micropower Shutdown: I

= 9µA

■

Tiny Low Profile (4mm × 4mm) QFN and Narrow

SSOP Packages

, LTC and LT are registered trademarks of Linear Technology Corporation.

The LTC

3736-1 is a 2-phase dual synchronous step-

down switching regulator controller with tracking that

drives external complementary power MOSFETs using

few external components. The constant frequency current

mode architecture with MOSFET V

sensing eliminates

the need for sense resistors and improves efficiency.

Power loss and noise due to the ESR of the input capaci-

tance are minimized by operating the two controllers out

of phase.

A unique spread spectrum architecture randomly varies

the LTC3736-1’s switching frequency from 450kHz to

580kHz, significantly reducing the peak radiated and con-

ducted noise on both the input and output supplies,

making it easier to comply with electromagnetic interfer-

ence (EMI) standards.

Pulse skipping operation provides high efficiency at light

loads. 100% duty cycle capability provides low dropout op-

eration, extending operating time in battery-powered sys-

tems. The high switching frequencies allow for the use of

small surface mount inductors and capacitors.

The LTC3736-1 is available in the low profile (0.75mm)

24-pin thermally enhanced (4mm × 4mm) QFN package

and 24-lead narrow SSOP packages.

No R

SENSE

is a trademark of Linear Technology Corporation.

Protected by U.S. Patents including 5481178, 5929620, 6144194, 6580258, 6304066,

6611131, 6498466.

■

One or Two Lithium-Ion Powered Devices

■

Notebook and Palmtop Computers, PDAs

■

Portable Instruments

■

Distributed DC Power Systems

SENSE1

LTC3736-1

SGND

SENSE2

TG1 TG2

SW1 SW2

BG1 BG2

PGND PGND

FB1

FB2

220pF

OUT1

2.5V

OUT2

1.8V

47µF

15k

220pF

15k

59k

187k

118k

2.2µH

TH1

37361 TA01a

TH2

10µF

×2

2.75V TO 9.8V

410k 450k 490k 530k 570k 610k

SPREAD SPECTRUM

ENABLED

SPREAD SPECTRUM

DISABLED

FREQUENCY (Hz)

–80

AMPLITUDE (dBm)

–20

–10

–90

–100

–30

–60

–40

–50

–70

37361 TA01b

–110

FIGURE 13 CIRCUIT

OUT

= 2.5V

= 30Hz

Output Voltage Frequency

Spectrum

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Summary of content (28 pages)

PAGE 1
LTC3736-1 Dual 2-Phase, No RSENSETM, Synchronous Controller with Spread Spectrum U FEATURES DESCRIPTIO ■ The LTC®3736-1 is a 2-phase dual synchronous stepdown switching regulator controller with tracking that drives external complementary power MOSFETs using few external components. The constant frequency current mode architecture with MOSFET VDS sensing eliminates the need for sense resistors and improves efficiency.
PAGE 2
LTC3736-1 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Supply Voltage (VIN) ........................ – 0.3V to 10V FREQ, RUN/SS, SSDIS, TRACK, SENSE1+, SENSE2+, IPRG1, IPRG2 Voltages ................. – 0.3V to (VIN + 0.3V) VFB1, VFB2, ITH1, ITH2 Voltages .................. – 0.3V to 2.4V SW1, SW2 Voltages ............ –2V to VIN + 1V or 10V Max PGOOD ..................................................... – 0.3V to 10V TG1, TG2, BG1, BG2 Peak Output Current (<10µs) .....
PAGE 3
LTC3736-1 ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified. PARAMETER CONDITIONS Output Voltage Load Regulation ITH = 0.9V (Note 5) ITH = 1.7V VFB1,2 Input Current (Note 5) TRACK Input Current TRACK = 0.6V Overvoltage Protect Threshold Measured at VFB MIN 0.66 Overvoltage Protect Hysteresis TYP MAX UNITS 0.12 –0.12 0.5 –0.
PAGE 4
LTC3736-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency and Power Lost vs Load Current 10 Load Step (Spread Spectrum Enabled) Load Step (Spread Spectrum Disabled) 100 FIGURE 13 CIRCUIT VIN = 5V 95 90 1 85 80 0.1 75 70 VOUT AC-COUPLED 100mV/DIV EFFICIENCY (%) POWER LOST (W) TA = 25°C unless otherwise noted. VOUT AC-COUPLED 100mV/DIV IL 2A/DIV IL 2A/DIV 65 0.01 60 VIN = 3.3V 100µs/DIV VOUT = 1.8V ILOAD = 300mA TO 3A SSDIS = GND FIGURE 15 CIRCUIT VOUT = 2.5V 55 VOUT = 1.
PAGE 5
LTC3736-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency and Power Lost vs Load Current 10 100 Efficiency vs Load Current 100 FIGURE 13 CIRCUIT VOUT = 2.5V POWER LOST (W) 20 0.1 75 70 VIN = 5V 60 VIN = 3.3V VIN = 4.2V 55 VIN = 7.2V 50 10 100 1000 10000 LOAD CURRENT (mA) 0.001 2 1 1.5 ITH VOLTAGE (V) 1 1.0 0.607 0.9 55 1 0.599 0.597 0.7 0.6 0.5 0.4 0.3 0.595 0.2 0.593 0.1 0 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 100 80 10 NORMALIZED FREQUENCY (%) 8 125 120 100 37361 G14 0.
PAGE 6
LTC3736-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Quiescent Current vs Input Voltage SHUTDOWN CURRENT (µA) RUN/SS Start-Up Current vs Input Voltage 0.9 RUN/SS = 0V RUN/SS PIN PULL-UP CURRENT (µA) 20 18 16 14 12 10 8 6 4 2 0 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 10 37361 G17 U U U PI FU CTIO S TA = 25°C unless otherwise noted. RUN/SS = 0V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.
PAGE 7
LTC3736-1 U U U PI FU CTIO S (UF/GN Package) TG1/TG2 (Pins 17, 15/Pins 20, 18): Top (PMOS) Gate Drive Output. These pins drive the gates of the external P-channel MOSFETs. These pins have an output swing from PGND to SENSE+. SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connection to Inductor. Also the negative input to differential peak current comparator and an input to the reverse current comparator.
PAGE 8
LTC3736-1 W FU CTIO AL DIAGRA U (Controller 1) U VIN SENSE1 + CIN RS1 CLK1 S TG1 MP1 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV1 SC1 PGND SW1 ANTISHOOT THROUGH L1 VOUT1 SENSE1+ COUT1 BG1 MN1 PGND SKIP1 IREV1 SLOPE1 SW1 – ICMP SENSE1+ + IPROG1 SHDN – + VFB1 R1B EAMP + R1A – 0.6V ITH1 EXTSS INTSS – RITH1 SKIP1 + 0.12V – VFB1 – PGND + SC1 0.15V OV1 – VFB1 + 0.
PAGE 9
LTC3736-1 W FU CTIO AL DIAGRA U (Controller 2) SENSE2+ RS2 CLK2 S VIN TG2 MP2 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV2 SC2 PGND SW2 ANTISHOOT THROUGH L2 VOUT2 SENSE2+ COUT2 BG2 MN2 PGND SKIP2 IREV2 SLOPE2 SW2 – ICMP SENSE2+ + SHDN – + R2B VFB2 EAMP + R2A VOUT1 – TRACK RTRACKB 0.6V RTRACKA ITH2 – RITH2 SKIP2 + SC2 + 0.12V – VFB2 – PGND CITH2 SCP 0.15V TRACK – OV2 VFB2 IREV2 OVP + + 0.
PAGE 10
LTC3736-1 U OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC3736-1 uses a current mode architecture with the two controllers operating 180 degrees out of phase. During normal operation, the top external P-channel power MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the current comparator (ICMP) resets the latch.
PAGE 11
LTC3736-1 U OPERATIO (Refer to Functional Diagram) operation enabled) with VIN = 5V, VOUT = 2.5V and IOUT = 1A. Note the significant reduction in peak output noise (>20dBm). Short-Circuit Protection When an output is shorted to ground (VFB < 0.12V), the switching frequency of that controller is reduced to 1/5 of the normal operating frequency. The other controller is unaffected and maintains normal operation. The short-circuit threshold on VFB2 is based on the smaller of 0.
PAGE 12
(Refer to Functional Diagram) The FREQ pin can be floated, tied to VIN or tied to SGND to select 550kHz, 750kHz or 300kHz respectively. The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage.
PAGE 13
LTC3736-1 U OPERATIO (Refer to Functional Diagram) on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. These large amplitude pulses increase the total RMS current flowing in the input capacitor, requiring the use of larger and more expensive input capacitors, and increase both EMI and power losses in the input capacitor and input power supply.
PAGE 14
LTC3736-1 U W U U APPLICATIO S I FOR ATIO The typical LTC3736-1 application circuit is shown in Figure 13. External component selection for each of the LTC3736-1’s controllers is driven by the load requirement and begins with the selection of the inductor (L) and the power MOSFETs (MP and MN). Power MOSFET Selection Each of the LTC3736-1’s two controllers requires two external power MOSFETs: a P-channel MOSFET for the topside (main) switch and an N-channel MOSFET for the bottom (synchronous) switch.
PAGE 15
LTC3736-1 U W U U APPLICATIO S I FOR ATIO less than 25nC to 30nC (at 4.5VGS) and a turn-off delay (tD(OFF)) of less than approximately 140ns. However, due to differences in test and specification methods of various MOSFET manufacturers, and in the variations in QG and tD(OFF) with gate drive (VIN) voltage, the P-channel MOSFET ultimately should be evaluated in the actual LTC3736-1 application circuit to ensure proper operation. ρT NORMALIZED ON RESISTANCE 2.0 1.5 1.0 0.
PAGE 16
LTC3736-1 U W U U APPLICATIO S I FOR ATIO Operating Frequency Inductor Value Calculation When spread spectrum operation is enabled (SSDIS = GND), the frequency of the LTC3736-1 is randomly varied over the range of frequencies between 450kHz and 580kHz. In this case, a capacitor (1nF to 4.7nF) should be connected between the FREQ pin and SGND (or VIN) to smooth out the changes in frequency.
PAGE 17
LTC3736-1 U W U U APPLICATIO S I FOR ATIO Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly.
PAGE 18
LTC3736-1 U W U U APPLICATIO S I FOR ATIO where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Setting Output Voltage The LTC3736-1 output voltages are each set by an external feedback resistor divider carefully placed across the output, as shown in Figure 6. The regulated output voltage is determined by: ⎛ R ⎞ VOUT = 0.
PAGE 19
LTC3736-1 U W U U APPLICATIO S I FOR ATIO The ramp time for VOUT2 to rise from 0V to its final value is: tSS2 = tSS1 • RTRACKA R1A + R1B • R1A RTRACKA + RTRACKB For coincident tracking, tSS2 = tSS1 • VOUT2F VOUT1F where VOUT1F and VOUT2F are the final, regulated values of VOUT1 and VOUT2. VOUT1 should always be greater than VOUT1 R1B VOUT2 LTC3736-1 VFB1 R2B VFB2 R1A R2A RTRACKB TRACK 37361 F08a RTRACKA Figure 8a.
PAGE 20
LTC3736-1 U W U U APPLICATIO S I FOR ATIO change as the supply is reduced down to 2.4V. Also shown is the effect on VREF. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time in which the LTC3736-1 is capable of turning the top P-channel MOSFET on and then off. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET.
PAGE 21
LTC3736-1 U W U U APPLICATIO S I FOR ATIO deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. modified slightly (from 0.
PAGE 22
LTC3736-1 U W U U APPLICATIO S I FOR ATIO at the FETs. It is better to have two separate, smaller valued input capacitors (e.g., two 10µF—one for each channel) than it is to have a single larger valued capacitor (e.g., 22µF) that the channels share with a common connection. 2) The signal and power grounds should be kept separate. The signal ground consists of the feedback resistor dividers, ITH compensation networks and the SGND pin.
PAGE 23
LTC3736-1 U TYPICAL APPLICATIO S RFB1B 562k CITH1A 100pF CITH1 220pF RITH1 15k 2200pF VIN 5V CIN 10µF ×2 22 23 24 1 2 3 4 RVIN 10Ω 5 CITH2 CVIN 220pF 1µF RITH2 15k CSS 10nF CITH2B 100pF RFB2A 453k 9 7 8 6 + 21 SW1 IPRG1 VFB1 ITH1 IPRG2 FREQ SENSE1 PGND BG1 SSDIS TG1 PGND SGND TG2 VIN RUN/SS LTC3736EUF-1 BG2 PGND PGOOD SENSE2+ VFB2 ITH2 TRACK SW2 PGND L1 1.5µH MP1 20 19 18 17 16 MN1 Si7540DP VOUT1 2.5V 5A + COUT1 150µF 15 14 13 12 11 MN2 Si7540DP MP2 10 + RFB1A 178k L2 1.
PAGE 24
LTC3736-1 U TYPICAL APPLICATIO S 68pF RFB1A 59k RFB1B 187k CITH1A 47pF 22 23 24 1 2 3 4 CITH1 470pF RITH1 22k 2200pF VIN 3.3V RVIN 10Ω 5 CIN 22µF 9 7 8 6 CITH2 CVIN 470pF 1µF RITH2 22k SENSE1+ PGND BG1 SSDIS TG1 PGND 15 TG2 14 VIN RUN/SS LTC3736EUF-1 13 BG2 12 PGND PGOOD + 11 SENSE2 VFB2 ITH2 10 TRACK SW2 PGND SW1 IPRG1 VFB1 ITH1 IPRG2 FREQ SGND CSS 10nF CITH2A 47pF RFB2A 59k L1 1.5µH MP1 21 20 19 18 17 16 MN1 Si7540DP COUT1 100µF COUT2 100µF MN2 Si7540DP MP2 VOUT1 2.5V 2A VOUT2 1.
PAGE 25
LTC3736-1 U TYPICAL APPLICATIO S CFF1 100pF RFB1B 187k CITH1 220pF RITH1 15k 2200pF VIN 3.3V RVIN 10Ω CIN 22µF CITH2 CVIN 220pF 1µF RITH2 15k RFB2A 59k RTRACKA 590Ω 4.7nF SSDIS 1 2 3 4 5 6 7 + 24 SW1 SENSE1 IPRG1 PGND BG1 VFB1 SSDIS ITH1 TG1 IPRG2 PGND FREQ TG2 SGND LTC3736EGN-1 5 VIN RUN/SS MP1 23 22 21 20 19 18 SW1 L1 1.5µH MN1 Si7540DP D1 MN2 Si7540DP D2 + COUT1 150µF 17 16 BG2 12 15 PGND PGOOD 10 14 SENSE2+ VFB2 11 ITH2 13 9 TRACK SW2 MP2 SW2 L2 1.5µH RFB2B RTRACKB 118k 1.
PAGE 26
LTC3736-1 U PACKAGE DESCRIPTIO UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ±0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.23 TYP R = 0.115 (4 SIDES) TYP 23 24 0.75 ± 0.05 PIN 1 TOP MARK (NOTE 6) 0.38 ± 0.10 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 1103 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1.
PAGE 27
LTC3736-1 U PACKAGE DESCRIPTIO GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .033 (0.838) REF .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ± .0015 2 3 4 5 6 7 8 9 10 11 12 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.
PAGE 28
LTC3736-1 U TYPICAL APPLICATIO 2-Phase, Spread Spectrum Dual Output, Synchronous DC/DC Converter RFB1A 59k RFB1B 187k CITH1A 100pF 2200pF VIN 5V CIN 10µF ×2 4 RVIN 10Ω 5 CITH2 CVIN 220pF 1µF RITH2 15k 9 7 8 6 SW1 IPRG1 VFB1 ITH1 IPRG2 FREQ PGND BG1 SSDIS TG1 PGND SGND TG2 VIN RUN/SS LTC3736EUF-1 BG2 PGND PGOOD SENSE2+ VFB2 ITH2 TRACK SW2 PGND CSS 10nF CITH2B 100pF RFB2A 59k 21 SENSE1+ L1 1.5µH MP1 20 19 18 17 16 VOUT1 2.