Datasheet

21
LTC3736-1
37361f
APPLICATIO S I FOR ATIO
WUUU
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and I
TH
pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing R
C
, and the bandwidth of the loop will be
increased by decreasing C
C
. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-1. These items are illustrated in the layout dia-
gram of Figure 11. Figure 12 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
SW1
IPRG1
V
FB1
I
TH1
IPRG2
FREQ
SGND
V
IN
TRACK
V
FB2
I
TH2
PGOOD
SENSE1
+
PGND
BG1
SSDIS
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
+
SW2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LTC3736EGN-1
+
+
C
OUT1
C
OUT2
C
VIN1
C
VIN
V
OUT1
V
OUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
37361 F11
L1
L2
MN1 MP1
MN2 MP2
V
IN
C
VIN2
Figure 11. LTC3736-1 Layout Diagram