Datasheet

LTC3780
25
Rev G
For more information www.analog.com
APPLICATIONS INFORMATION
• Use immediate vias to connect the components (in-
cluding the LTC3780’
s SGND and PGND pins) to the
ground plane. Use several large vias for each power
component.
• Use planes for V
IN
and V
OUT
to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(V
IN
or GND).
• Segregate the signal and power grounds. All small-
signal components should return to the SGND pin at
one point, which is then tied to the PGND pin close to
the sources of switch B and switch C.
• Place switch B and switch C as close to the controller as
possible, keeping the PGND, BG and SW traces short.
• Keep the high dV/dT SW1, SW2, BOOST1, BOOST2,
TG1 and TG2 nodes away from sensitive small-signal
nodes.
• The path formed by switch A, switch B, D1 and the C
IN
capacitor should have short leads and PC trace lengths.
The path formed by switch C, switch D, D2 and the
C
OUT
capacitor also should have short leads and PC
trace lengths.
• The output capacitor (–) terminals should be connected
as close as possible the (–) terminals of the input
capacitor.
•
Connect the top driver boost capacitor C
A
closely to the
BOOST1 and SW1 pins. Connect the top driver boost
capacitor C
B
closely to the BOOST2 and SW2 pins.
• Connect the input capacitors C
IN
and output capacitors
C
OUT
closely to the power MOSFETs. These capacitors
carry the MOSFET AC current in boost and buck mode.
• Connect V
OSENSE
pin resistive dividers to the (+) termi-
nals of C
OUT
and signal ground. A small V
OSENSE
bypass
capacitor may be connected closely to the LTC3780
SGND pin. The R2 connection should not be along the
high current or noise paths, such as the input capaci
-
tors.
•
Route SENSE
–
and SENSE
+
leads together with minimum
PC trace spacing. Avoid sense lines pass through noisy
area, such as switch nodes. The filter capacitor between
SENSE
+
and SENSE
–
should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor. One layout example
is shown in Figure 12.
• Connect the I
TH
pin compensation network close to the
IC, between I
TH
and the signal ground pins. The capaci-
tor helps to filter the effects of PCB noise and output
voltage ripple voltage from the compensation loop.
•
Connect the INTV
CC
bypass capacitor, C
VCC
, close to the
IC, between the INTV
CC
and the power ground pins. This
capacitor carries the MOSFET drivers’ current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve
noise performance substantially.
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