Datasheet

LTC3824
7
3824fh
For more information www.linear.com/LTC3824
pin FuncTions
GND (Pin 1, Exposed Pad Pin 11): Ground. Exposed pad
must be soldered to PCB with expanded metal trace for
rated thermal performance.
SYNC/MODE (Pin 2): Synchronization Input and Burst
Mode Operation Enable/Disable. If this pin is left open
or pulled higher than 2V, Burst Mode operation will be
enabled at light load and the typical threshold of entering
Burst Mode operation is one third of current limit. If this
pin is grounded or the synchronization pulse is present
with a frequency greater than 20kHz then Burst Mode
operation is disabled and the LTC3824 goes into pulse
skipping at light loads. To synchronize the LTC3824, the
duty cycle of the synchronizing pulse can range from 10%
to 70% and the synchronizing frequency has to be higher
than the programmed frequency.
R
SET
(Pin 3): A resistor from R
SET
to ground sets the
LTC3824 switching frequency.
V
C
(Pin 4): The Output of the voltage error amplifier gm
and the control signal of the current mode PWM control
loop. Switching starts at 0.7V, and higher V
C
corresponds
to higher inductor current. When V
C
is pulled below 25mV,
the LTC3824 goes into micropower shutdown.
V
FB
(Pin 5): Error Amplifier Inverting Input. A resistor
divider to this pin sets the output voltage. When V
FB
is
less than 0.5V, the switching frequency will fold back to
50kHz to reduce the minimum on-cycle.
SS (Pin 6): Soft-Start Pin. A capacitor on this pin sets
the output ramp-up rate. The typical time for SS to
reach the programmed level is (C • 0.8V)/5µ
A . Connect
a 1MΩ to 10MΩ resistor from SS to ground to reset
the soft-start capacitor if shutdown mode is used.
SENSE (Pin 7): Current Sense Input Pin. A sense re-
sistor, R
S
, from V
IN
to SENSE sets the current limit to
100mV/R
S
.
V
CC
(Pin 8): Chip Power Supply. Power supply bypass-
ing is required.
GATE (Pin 9): Gate Drive for The External P-channel
MOSFET. Typical peak drive current is 2.5A and the drive
voltage is clamped to 8V when V
CC
is higher than 9V.
CAP (Pin 10): A Low ESR Capacitor of at Least 0.1µF is
required from this pin to V
CC
to bypass the internal regula-
tor for biasing the gate driver circuitry.
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