Datasheet

7
LTC3832/LTC3832-1
sn3832 3832fs
UU
U
PI FU CTIO S
FREQSET (Pin 11/NA): Frequency Set. Use this pin to
adjust the free-running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 300kHz.
A resistor from FREQSET to ground speeds up the oscil-
lator; a resistor to V
CC
slows it down.
I
MAX
(Pin 12/NA): Current Limit Threshold Set. I
MAX
sets
the threshold for the internal current limit comparator. If
I
FB
drops below I
MAX
with G1 on, the LTC3832 goes into
current limit. I
MAX
has an internal 12µA pull-down to GND.
Connect this pin to the main V
IN
supply at the drain of Q1,
through an external resistor to set the current limit thresh-
old. Connect a 0.1µF decoupling capacitor across this
resistor to filter switching noise.
I
FB
(Pin 13/NA): Current Limit Sense. Connect this pin to
the switching node at the source of Q1 and the drain of Q2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging I
FB
.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
V
CC
(Pin 14/Pin 7): Power Supply Input. All low power
internal circuits draw their supply from this pin. Connect
this pin to a clean power supply, separate from the main
V
IN
supply at the drain of Q1. This pin requires a 4.7µF
bypass capacitor. The LTC3832-1has V
CC
and PV
CC2
tied
together at Pin 7 and requires a 10µF bypass capacitor to
GND.
PV
CC2
(Pin 15/Pin 7): Power Supply Input for G2. Connect
this pin to the main high power supply.
G2 (Pin 16/Pin 8): Bottom Gate Driver Output. Connect
this pin to the gate of the lower N-channel MOSFET, Q2.
This output swings from PGND to PV
CC2
. It remains low
when G1 is high or during shutdown mode. To prevent
output undershoot during a soft-start cycle, G2 is held low
until G1 first goes high (FFBG in the Block Diagram).
BLOCK DIAGRA
W
–
+
–
+
R
S
PV
CC1
G1
PV
CC2
G2
PGND
FB
SENSE
+
V
REF
V
REF
+ 10%
18k
5.7k
SENSE
–
3832 BD
BG
Q
Q
RPOR
S
FFBG
ENABLE
G2
Q
–
+
PWM
QSS
V
REF
V
REF
+ 10%
MAX
ERR
12µA
INTERNAL
OSCILLATOR
100µs DELAY
SHDN
FREQSET
COMP
SS
POWER DOWN
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
+
–
CC
2.2V
QC
1.2V
PV
CC1
V
CC
+ 2.5V
12µA
DISABLE
I
LIM
I
MAX
I
FB
V
CC
GND
–
+
V
(LTC3832)