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LTC3834-1

38341f

30μA I

Synchronous

Step-Down Controller

High Efficiency Step-Down Converter

■

Wide Output Voltage Range: 0.8V V

OUT

10V

■

Low Operating I

: 30μA

■

OPTI-LOOP

Compensation Minimizes C

OUT

■

±1% Output Voltage Accuracy

■

Wide V

Range: 4V to 36V

■

Phase-Lockable Fixed Frequency 140kHz to 650kHz

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Dual N-Channel MOSFET Synchronous Drive

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Very Low Dropout Operation: 99% Duty Cycle

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Adjustable Output Voltage Soft-Start or Tracking

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Output Current Foldback Limiting

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Output Overvoltage Protection

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Low Shutdown I

: 4μA

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Selectable Continuous, Pulse-Skipping or

Burst Mode

Operation at Light Loads

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Small 16-Lead Narrow SSOP or 5mm × 3mm

DFN Package

The LTC

3834-1 is a high performance step-down switch-

ing regulator controller that drives an all N-channel syn-

chronous power MOSFET stage. A constant-frequency

current mode architecture allows a phase-lockable fre-

quency of up to 650kHz.

The 30μA no-load quiescent current extends operating

life in battery powered systems. OPTI-LOOP compen-

sation allows the transient response to be optimized over

a wide

range of output capacitance and ESR values. The

LTC3834-1

features a precision 0.8V reference . The 4V to

36V input supply range encompasses a wide range of bat-

tery chemistries.

The TRACK/SS pin ramps the output voltage during start-

up. Current foldback limits MOSFET heat dissipation

during short-circuit conditions. An enhanced feature set

part (LTC3834) is available.

Comparison of LTC3834 and LTC3834-1

CLKOUT/

PART # PHASMD EXTV

PGOOD PACKAGES

LTC3834 YES YES YES FE20/4 × 5 QFN

LTC3834-1 NO NO NO GN16/3 × 5 DFN

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Automotive Systems

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Telecom Systems

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Battery-Operated Digital Devices

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Distributed DC Power Systems

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

Efficiency and Power Loss

vs Load Current

, LT, LTC, LTM, Burst Mode, PolyPhase and OPTI-LOOP are registered trademarks of

Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents, including 5408150, 5481178, 5705919, 5929620,

6304066, 6498466, 6580258, 6611131.

OUTPUT CURRENT (A)

EFFICIENCY (%)

POWER LOSS (mW)

0.0001 0.01 1

38341 TA01b

0.000001

1000

100

0.1

10000

100

OUT

3.3V

150μF

0.01μF

4V TO 36V

SGND

PLLIN/MODE

SENSE

–

PLLLPF

RUN

TRACK/SS

INTV

PGND

LTC3834-1

3.3μH

0.012Ω

68.1k

38341 TA01

150pF

560pF

54.2k

215k

4.7μF

0.22μF

BOOST

10μF

Summary of content (28 pages)

PAGE 1
LTC3834-1 30μA IQ Synchronous Step-Down Controller U FEATURES DESCRIPTIO ■ The LTC®3834-1 is a high performance step-down switching regulator controller that drives an all N-channel synchronous power MOSFET stage. A constant-frequency current mode architecture allows a phase-lockable frequency of up to 650kHz. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Wide Output Voltage Range: 0.
PAGE 2
LTC3834-1 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Supply Voltage (VIN).........................36V to – 0.3V Top Side Driver Voltage (BOOST) ..............42V to – 0.3V Switch Voltage (SW) ....................................36V to – 5V INTVCC, (BOOST-SW).................................8.5V to – 0.3V RUN, TRACK/SS ......................................... 7V to – 0.3V SENSE+, SENSE– Voltages .........................11V to – 0.3V PLLIN/MODE, PLLLPF ......................... INTVCC to – 0.
PAGE 3
LTC3834-1 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; I TH Voltage = 1.2V to 0.7V Measured in Servo Loop; I TH Voltage = 1.2V to 2V MIN gm Transconductance Amplifier gm ITH = 1.2V; Sink/Source 5μA (Note 4) 0.
PAGE 4
LTC3834-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency and Power Loss vs Output Current 80 EFFICIENCY (%) 90 1000 100 60 50 10 40 30 POWER LOSS (mW) 70 Burst Mode OPERATION FORCED CONTINUOUS MODE PULSE SKIPPING MODE VIN = 12V VOUT = 3.3V 100 1 20 Efficiency vs Input Voltage 98 VIN = 12V VIN = 5V VOUT = 3.3V 96 94 80 EFFICIENCY (%) 90 Efficiency vs Load Current 10000 EFFICIENCY (%) 100 TA = 25ºC, unless otherwise noted. 70 60 92 90 88 86 84 VOUT = 3.
PAGE 5
LTC3834-1 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Input Supply Current vs Input Voltage TA = 25ºC, unless otherwise noted. INTVCC Voltages vs Temperature 350 INTVCC Line Regulation 5.5 6.0 FIGURE 10 CIRCUIT 5.8 300 5.4 200 150 300μA LOAD 100 INTVCC 5.2 5.0 4.8 4.6 5.3 5.2 5.1 4.4 NO LOAD 50 5.4 INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) SUPPLY CURRENT (μA) 5.6 250 4.2 0 5 20 25 15 INPUT VOLTAGE (V) 10 30 4.0 –45 35 5.
PAGE 6
LTC3834-1 U W TYPICAL PERFOR A CE CHARACTERISTICS TRACK/SS Pull-Up Current vs Temperature SENSE Pins Total Input Bias Current vs ITH 3 2 1 Shutdown (RUN) Threshold vs Temperature 1.30 1.00 1.25 0.95 0.90 1.20 RUN PIN VOLTAGE (V) TRACK/SS CURRENT (μA) 4 INPUT CURRENT (μA) TA = 25ºC, unless otherwise noted. 1.15 1.10 1.05 1.00 0.85 0.80 0.75 0.70 0.65 0.60 0.95 0 0 0.2 0.4 0.6 0.8 1.0 ITH VOLTAGE (V) 1.2 0.55 0.90 –45 –30 –15 1.
PAGE 7
LTC3834-1 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25ºC, unless otherwise noted. INTVCC vs Load Current Shutdown Current vs Temperature 5.3 7 VIN = 12V 6 SHUTDOWN CURRENT (μA) INTVCC VOLTAGE (V) 5.2 5.1 5.0 4.9 4.8 5 4 3 2 1 4.7 4.
PAGE 8
LTC3834-1 U U U PI FU CTIO S (DHC Package/GN Package) ler functions, reducing the quiescent current that the LTC3834-1 draws to approximately 4μA. phase-locked loop will force the rising TG signal to be synchronized with the rising edge of the external clock. In this case, an R-C filter must be connected to the PLLLPF pin. When not synchronizing to an external clock, this input determines how the LTC3834-1 operates at light loads. Pulling this pin below 0.7V selects Burst Mode operation.
PAGE 9
LTC3834-1 U OPERATIO (Refer to Functional Diagram) Main Control Loop Shutdown and Start-Up (RUN and TRACK/SS Pins) The LTC3834-1 uses a constant-frequency, current mode step-down architecture. During normal operation, each external top MOSFET is turned on when the clock sets the RS latch, and is turned off when the main current comparator, ICMP, resets the RS latch.
PAGE 10
LTC3834-1 U OPERATIO (Refer to Functional Diagram) Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction) (PLLIN/MODE Pin) The LTC3834-1 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to a DC voltage below 0.8V (e.g., SGND). To select forced continuous operation, tie the PLLIN/ MODE pin to INTVCC.
PAGE 11
LTC3834-1 U OPERATIO (Refer to Functional Diagram) The typical capture range of the LTC3834-1’s phaselocked loop is from approximately 115kHz to 800kHz, with a guarantee to be between 140kHz and 650kHz. In other words, the LTC3834-1’s PLL is guaranteed to lock to an external clock source whose frequency is between 140kHz and 650kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling).
PAGE 12
LTC3834-1 U W U U APPLICATIO S I FOR ATIO Accepting larger values of I L allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is I L=0.3(IMAX). The maximum I L occurs at the maximum input voltage. The inductor value also has secondary effects.
PAGE 13
LTC3834-1 U W U U APPLICATIO S I FOR ATIO The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT 2 IMAX ) (1+ δΔT )RDS(ON) + ( VIN ( VIN )2 ⎛⎜⎝ IM2AX ⎞⎟⎠ (RDR )(CMILLER ) • ⎡ 1 1 ⎤ + ⎢ ⎥ ( f) ⎣ VINTVCC – VTHMIN VTHMIN ⎦ PSYNC = VIN – VOUT 2 IMAX ) (1+ δΔT )RDS(ON) ( VIN where δ is the temperature dependency of RDS(ON) and RDR (approximately 2 ) is the effective driver resistance at the MOSFET’s Miller threshold voltage.
PAGE 14
LTC3834-1 U W U U APPLICATIO S I FOR ATIO 60 Setting Output Voltage 30 VOUT ⎛ R ⎞ = 0.8V • ⎜ 1+ B ⎟ ⎝ RA ⎠ 0 INPUT BIAS CURRENT (μA) The LTC3834-1 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 1. The regulated output voltage is determined by: –30 –60 –90 –120 –150 –180 –210 –240 –270 To improve the frequency response, a feed-forward capacitor, CFF, may be used.
PAGE 15
LTC3834-1 U W U U APPLICATIO S I FOR ATIO Alternatively, the TRACK/SS pin can be used to track two (or more) supplies during start-up, as shown qualitatively in Figures 4a and 4b. To do this, a resistor divider should be connected from the master supply (VX) to the TRACK/ SS pin of the slave supply (VOUT), as shown in Figure 5.
PAGE 16
LTC3834-1 U W U U APPLICATIO S I FOR ATIO High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3834-1 to be exceeded. The INTVCC current, which is dominated by the gate charge current, is supplied by the 5.25V VIN LDO. Power dissipation for the IC in this case is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section.
PAGE 17
LTC3834-1 U W U U APPLICATIO S I FOR ATIO Phase-Locked Loop and Frequency Synchronization The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating frequency, when there is a clock signal applied to PLLIN/ MODE, is shown in Figure 6 and specified in the Electrical Characteristics table.
PAGE 18
LTC3834-1 U W U U APPLICATIO S I FOR ATIO If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin.
PAGE 19
LTC3834-1 U W U U APPLICATIO S I FOR ATIO Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power.
PAGE 20
LTC3834-1 U W U U APPLICATIO S I FOR ATIO Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to I LOAD (ESR), where ESR is the effective series resistance of COUT.
PAGE 21
LTC3834-1 U W U U APPLICATIO S I FOR ATIO Design Example As a design example, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A, and f = 250kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLLPF pin to GND, generating 250kHz operation. The minimum inductance for 30% ripple current is: ΔIL = ⎞ VOUT ⎛ V 1 – OUT ⎟ ⎜ ( f)(L) ⎝ VIN ⎠ A 4.
PAGE 22
LTC3834-1 U W U U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 8. The Figure 9 illustrates the current waveforms present in the various branches of the synchronous regulator operating in the continuous mode. Check the following in your layout: 1.
PAGE 23
LTC3834-1 U W U U APPLICATIO S I FOR ATIO SW VIN L1 RSENSE VOUT RIN CIN D1 COUT RL1 3834-1 F09 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. Figure 9. Branch Current Waveforms PC Board Layout Debugging It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well.
PAGE 24
LTC3834-1 U TYPICAL APPLICATIO S High Efficiency 9.5V, 3A Step-Down Converter PLLLPF TG RUN 0.01μF VIN TRACK/SS CB 0.22μF L1 7.2μH BOOST ITH 560pF LTC3834-1 CIN 10μF M1 0.015Ω SW VIN 10V TO 36V VOUT 9.5V 3A 100pF 105k SGND 39.2k COUT 150μF INTVCC 4.7μF PLLIN/MODE VFB M2 BG SENSE– 432k SENSE+ 22pF PGND 38341 TA02 M1, M2: Si4840DY L1: CDEP105-7R2M COUT: SANYO 10TPD150M High Efficiency 12V to 1.8V, 2A Step-Down Converter PLLLPF TG RUN 0.01 VIN TRACK/SS CB 0.
PAGE 25
LTC3834-1 U TYPICAL APPLICATIO S High Efficiency 5V, 5A Step-Down Converter VIN PLLLPF TG RUN 0.01μF TRACK/SS M1 CB 0.22μF L1 3.3μH BOOST ITH 560pF CIN 10μF 0.012Ω SW LTC3834-1 150pF 54k SGND 69.8k VIN 5.5V TO 36V VOUT 5V 5A COUT 150μF INTVCC 4.7μF PLLIN/MODE VFB M2 BG SENSE– 365k 39pF SENSE+ PGND 38341 TA04 M1, M2: Si4840DY L1: CDEP105-3R2M COUT: SANYO 10TPD150M High Efficiency 1.2V, 5A Step-Down Converter GND PLLLPF TG RUN 0.01μF VIN TRACK/SS M1 CB 0.22μF L1 2.
PAGE 26
LTC3834-1 U PACKAGE DESCRIPTIO DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) 0.65 ±0.05 3.50 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 4.40 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5.00 ±0.10 (2 SIDES) R = 0.20 TYP 3.00 ±0.10 (2 SIDES) 9 0.40 ± 0.10 16 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH (DHC16) DFN 1103 8 0.200 REF 1 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 4.40 ±0.10 (2 SIDES) 0.
PAGE 27
LTC3834-1 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .0532 – .0688 (1.35 – 1.75) 2 3 4 5 6 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.
PAGE 28
LTC3834-1 U TYPICAL APPLICATIO PLLLPF TG RUN 0.01μF VIN TRACK/SS VIN 4V TO 36V CIN 10μF CB 0.22μF BOOST ITH 560pF LTC3834-1 SW DB CMDSH-3 150pF 54k SGND 68.1k VOUT 3.3V 5A 0.012Ω INTVCC COUT 150μF 4.7μF PLLIN/MODE VFB L1 3.2μH BG SENSE– 215k SENSE+ PGND 39pF 38341 TA06 M1, M2: Si4840DY L1: CDEP 105-3R2M COUT: SANYO 10TPD150M Figure 10. High Efficiency 3.