Datasheet

LTC4020
31
4020fd
For more information www.linear.com/LTC4020
During an NTC fault, charging is halted and an NTC fault
is indicated on the status pins. If timer termination is en-
abled, the timer count is suspended and held until the fault
condition is relieved
.
The RNG/SS pin is also pulled low
during this fault, to accommodate a graceful restart, in the
event that a soft-start function is being incorporated (see
Dynamic Charge Current Adjust and Soft-Start section).
DC/DC Converter: External Compensation and
Filtering Components
The LTC4020 average current mode architecture employs
two integrating compensation nodes. The current setting
loop is compensated at the output of the current sense
amplifier on the VC pin, generally with a series R-C net
-
work (
R
VC
, C
VC
). The voltage generated on the VC pin is
compared with an internal ramp, providing control of the
converter duty cycle.
The voltage loop is compensated at the output of the error
amplifier on the ITH pin, generally with a series R-C net-
work (R
ITH
, C
ITH
). The voltage on the ITH pin is imposed
onto the current sense amplifier, setting the current level
to which the current loop will servo.
While determining compensation components, the
LTC4020 should initially be configured to eliminate any
functional contribution from the battery charger section.
This can be easily accomplished by connecting the NTC pin
to ground, which disables all battery charging functions
and puts the PowerPath FET into a high impedance state.
The current loop compensation (VC pin) transfer function
crossover frequency is typically set to approximately one-
half of the switching frequency; the voltage loop compen-
sation (ITH pin) transfer function crossover frequency is
typically set to approximately one-tenth of the switching
frequency.
Compensation values must be tested at high and low
input voltage operational limits, and also V
IN
~ V
OUT
, so
that stable operation during all switching modes (buck,
boost, buck-boost) is verified.
If a network analyzer is not available for determining
compensation values, use procedures as outlined in
Application Note 19 for adjusting compensation. Appli-
cation Note 19 can be found at http://www.linear.com/
docs/4176
.
VC pin compensation:
1. V
NTC
= V
FBMAX
= 0V
2. Fix V
IN
at typical voltage.
3. Fix V
OUT
at V
FB
regulation voltage. A charged battery,
battery simulator, or a 2-quadrant power supply can
be used for V
OUT
.
4. Impose 1V to 1.5V square wave (1kHz) on ITH pin
5. Monitor inductor current using current probe
6. Adjust compensation values as per AN19 until response
is critically damped
ITH pin compensation:
1. V
NTC
= 0V (disables charger)
2. Bring to regulation (V
FBMAX
= 2.75V)
3. Step load current on output (25% to 75% of I
MAX
)
4. Monitor V
OUT
voltage
5. Adjust compensation values as per AN19 until response
is critically damped and settled in ~10 to 25 cycles
6. V
NTC
= 0.8 (enable charger)
7. Exercise battery charger and verify stability in all modes
Battery Charger Functions: Filtering Components
Voltage Regulation Loop (VFB):
The charger voltage regulation loop monitors battery
voltage, and as such is controlled by a very slow moving
node. Battery ESR, however, can produce significant AC
voltages due to ripple currents, which can cause unstable
operation. This ESR effect can be reduced by adding a
capacitor to the VFB input, producing a low frequency pole.
applicaTions inForMaTion
Figure 18. VFB Ripple Suppression
4020 F18
V
BAT
R
FB1
R
FB2
VFB
LTC4020
C
VFB
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