Datasheet

LTC4020
33
4020fd
For more information www.linear.com/LTC4020
During the dead time between synchronous switch and
main switch conduction, the body diode of the synchronous
FET conducts inductor current. Commutating the body
diode requires a significant charge contribution from the
main switch during initiation of main switch, creating a
current spike in the main switch. At the instant the body
diode commutates, a current discontinuity is created
between the inductor and main switch, with parasitic
inductance causing the switch node to transition in
response to this discontinuity
.
High currents and exces-
sive parasitic inductance can generate extremely fast δV/
δ
t times during this transition
. These fast δV/δt transi-
tions can sometimes cause avalanche breakdown in the
synchronous FET body diode
,
generating shoot-through
currents via parasitic turn-on of the synchronous FET.
Layout practices and component orientations that minimize
parasitic inductance on the switched nodes is critical for
reducing these effects.
Orient power path components such that current paths in
the ground plane do not cross through signal ground areas.
Power ground currents are controlled on the LTC4020
via the PGND pin, and this ground references the high
current synchronous switch drive components, as well
as the local INTV
CC
supply. It is important to keep PGND
and SGND voltages consistent with each other. Separat-
ing these grounds with thin traces is not recommended.
When a ground referenced switch FET is turned off
,
gate
drive currents return to the LTC4020 PGND pin from the
switch FET source. The BOOST supply refresh surge cur
-
rents also return through this same path. The switch FETs
must be oriented such that these PGND return currents
do not corrupt the SGND reference.
applicaTions inForMaTion
The high δi/δt loop formed by the switch MOSFETs and
the input capacitor (CV
IN
) should have short wide traces
to minimize high frequency noise and voltage stress
from inductive ringing. Surface mount components are
preferred to reduce parasitic inductances from component
leads. Switch path currents can be controlled by orient
-
ing switch FETs, the switched inductor, and input and
output decoupling capacitors in close proximity to each
other
.
Locate the INTV
CC
, BST1, and BST2 decoupling
capacitors in close proximity to the IC. These capacitors
carry the switch FET gate drive currents. Locate the small
signal components away from high frequency switching
nodes (TG1, BG1, TG2, BG2, SW1, SW2, BST1, BST2,
and INTV
CC
). High current switching nodes are oriented
across the top of the LTC4020 package to simplify layout
and prevent corruption of the SGND reference.
Locate the output and battery charger feedback resistors
in close proximity to the LTC4020 and minimize the length
of the high impedance feedback nodes.
The SENSVIN and SENSTOP traces should be routed
together and SENSBOT and SENSGND should be routed
together. Keep these traces as short as possible, and avoid
corruption of these lines by high current switching nodes.
The LTC4020 packaging has been designed to efficiently
remove heat from the IC via the exposed pad on the
backside of the package. The exposed pad is soldered to
a copper footprint on the PCB. The exposed pad is electri
-
cally connected to SGND, so a good connection to a PCB
ground plane effectively reduces the thermal resistance
of the IC case to ambient air
.
Please refer
to LTC Application Note 136, which discusses
guidelines, techniques, and considerations for switching
power supply PCB design and layout: http://www.linear.
com/docs/42146.
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