Datasheet

LTC4020
8
4020fd
For more information www.linear.com/LTC4020
pin FuncTions
TG1 (Pin 1): V
IN
side (step-down) primary switch FET
gate driver output.
BST1 (Pin 2): Boosted supply rail for V
IN
side (step-down)
switch FETs. Connect 1µF capacitor from this pin to SW1.
Connect 1A Schottky diode cathode to this pin, anode to
INTV
CC
pin.
SENSGND (Pin 4): Kelvin connection for PGND used for
SENSBOT current sense reference.
SENSBOT (Pin 5): Ground Referred Current Sense Amplifier
Input. Inductor current is monitored via a PGND referenced
current sense resistor (R
SENSEB
), typically in series with
the source of the V
IN
side synchronous switch FET. Kelvin
connect this pin to the associated sense resistor. Inductor
current is limited to a maximum average value (I
LMAX
), and
corresponds to 50mV across this sense resistor during
normal operation.
R
SENSEB
= 0.05/I
LMAX
Set R
SENSEB
= R
SENSEA
, as described in SENSTOP pin
description. A filter capacitor (C
SENSB
) is typically con-
nected from SENSBOT to SENSGND for noise reduction.
C
SENSB
~ 1nS/R
SENSEB
See Applications Information section.
SENSTOP (Pin 6): V
IN
Referred Current Sense Amplifier
Input. Inductor current is monitored via a V
IN
referenced
current sense resistor (R
SENSEA
), typically in series with
the drain of the V
IN
side primary switch FET. Kelvin con-
nect this pin to the associated sense resistor. Inductor
current is limited to a maximum average value (I
LMAX
),
and corresponds to 50mV across this sense resistor dur-
ing normal operation.
R
SENSEA
= 0.05/I
LMAX
Set R
SENSEA
= R
SENSEB
, as described in SENSBOT pin
description.
SENSVIN (Pin 7): Kelvin connection for input supply (V
IN
)
used for SENSTOP current sense reference. Input power
supply pin for most internal low current functions. Typical
pin bias current is 0.25mA.
RT (Pin 8): System Oscillator Frequency Control Pin.
Connect resistor (R
RT
) from this pin to ground. Resistor
value can range from 50kΩ (500khz) to 500kΩ (50khz).
R
RT
= 100kΩ yields 250kHz operating frequency. See
Applications Information.
SHDN (Pin 9): Precision Threshold Shutdown Pin. En
-
able threshold is 1.225V (rising), with 100mV of input
hysteresis. When in shutdown, all charging functions are
disabled and input supply current is reduced to 27.5µA.
Typical SHDN pin input bias current is 10nA.
V
IN_REG
(Pin 10): Input Voltage Regulation Reference.
Battery charge current is reduced when the voltage on
this pin falls below 2.5V. Connecting a resistor divider
from V
IN
to this pin enables programming of minimum
operational V
IN
voltage for the battery charging function.
This is used to program the peak power voltage for a
solar panel, or to help maintain a minimum voltage on
a poorly regulated input supply. This pin should not be
used to program minimum operational V
IN
voltage with
low impedance supplies. Should the input supply begin to
collapse, the LTC4020 reduces the DC/DC converter input
power such that programmed minimum V
IN
operational
voltage is maintained. If the voltage regulation feature is
not used, connect the V
IN_REG
pin to V
IN
or INTV
CC
. Typical
V
IN_REG
pin input bias current is 10nA. See Applications
Information.
MODE (Pin 11): Charger Mode Control Pin. Short this pin
to ground to enable a constant-current/constant-voltage
(CC/CV) charging algorithm. Connect this pin to pin INTV
CC
to enable a 4-step, 3-stage lead-acid charging algorithm.
Float this pin to force a constant-current (CC) charging
function. See Applications Information section.
STAT1 (Pin 12): Open-collector status output, typically
pulled up through a resistor to a supply voltage
. This status
pin can be pulled up to voltages as high as 55V when the
pin is disabled, and can sink currents up to 1mA when logic
low (<0.4V). Pull down currents as high as 5mA (absolute
maximum) are supported for higher current applications,
such as lighting LEDs.
If the LTC4020 is configured for a CC/CV charging algo
-
rithm, the STAT1 pin is pulled low while battery charge
currents exceed
10%
of the programmed maximum (C/10).
The STAT1 pin is also pulled low during NTC faults. The
STAT1 pin becomes high impedance when a charge cycle
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