Datasheet

LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
23
425212fe
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applicaTions inForMaTion
satisfied before a GATE start-up cycle begins. SS ramps up
as dictated by R
SS
•C
SS
; GATE is held low by the analog
current limit amplifier until SS crosses 20 • V
OS
. Upon
releasing GATE, 58µA sources into the external MOSFET
gate and compensation network. When the GATE voltage
reaches the MOSFET’s threshold, current begins flowing
into the load capacitor at time point 5. At time point 6,
load current reaches the SS control level and the analog
current limit loop activates. Between time points 6 and 8,
the GATE voltage is servoed, the SENSE voltage is regulated
at V
ACL
(t) and soft-start limits the slew rate of the load
current. If the SENSE voltage (V
SENSE
– V
EE
) reaches the
V
CB
threshold at time point 7, the circuit breaker TIMER
activates. The TIMER capacitor, C
T
, is charged by a (230µA
+ 8 • I
DRN
) current pull-up. As the load capacitor nears full
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below V
ACL
(t).
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below V
CB
and the fault TIMER cycle ends, followed by a
5.8µA discharge cycle (cool off). When GATE ramps past
V
GATEH
threshold at time point 10, PWRGD pulls low. At
time point 11, GATE reaches its maximum voltage as
determined by V
IN
.
5.8µA
58µA
5.8µA
5.8µA
58µA
GATE
START-UP
INITIAL TIMING
UV CLEARS V
UVHI
, CHECK OV < V
OVHI
, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 • V
OS
AND TIMER < V
TMRL
1 2 3 4 56 7 8 9
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
, SENSE < V
CB
AND SS < 20 • V
OS
1011
425212 F10
GND – V
EE
OR
(–48RTN) – (–48V)
UV/OV
V
IN
TIMER
GATE
SENSE
V
OUT
SS
DRAIN
PWRGD
V
LKO
V
UVHI
V
ACL
V
CB
230µA + 8 • I
DRN
20 • V
OS
V
IN
– V
GATEH
V
DRNL
V
DRNCL
20 • (V
CB
+ V
OS
)
20 • (V
ACL
+ V
OS
)
V
GATEL
V
TMRL
V
TMRH
Figure 10. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to V
EE
)