Datasheet

LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
22
425212fe
For more information www.linear.com/LTC4252-1
applicaTions inForMaTion
At time point 8, the load current falls and the SENSE voltage
drops below V
ACL
(t). The analog current limit loop shuts
off and the GATE pin ramps further. At time point 9, the
SENSE voltage drops below V
CB
, the fault TIMER cycle
ends, followed by a 5.8µA discharge cycle (cool off). The
duration between time points 7 and 9 must be shorter than
one circuit breaker delay to avoid a fault time out during
GATE ramp-up. When GATE ramps past the V
GATEH
thresh-
old at time point 10, PWRGD pulls low. At time point11,
GATE reaches its maximum voltage as determined by V
IN
.
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 10, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4252 is
activated. At time point 1, the power pins make contact
and V
IN
ramps through V
LKO
. At time point 2, the UV/OV
divider makes contact and its voltage exceeds V
UVHI
. In
addition, the internal logic checks for OV < V
OVHI
, GATE
< V
GATEL
, SENSE < V
CB
, SS < 20 • V
OS
and TIMER <
V
TMRL
. If all conditions are met, an initial timing cycle
starts and the TIMER capacitor is charged by a 5.8µA
current source pull-up. At time point 3, TIMER reaches the
V
TMRH
threshold and the initial timing cycle terminates.
The TIMER capacitor is quickly discharged. At time point
4, the V
TMRL
threshold is reached and the conditions of
GATE < V
GATEL
, SENSE < V
CB
and SS < 20 • V
OS
must be
GND – V
EE
OR
(–48RTN) – (–48V)
UV/OV
V
IN
TIMER
GATE
V
LKO
SENSE
V
IN
CLEARS V
LKO
, CHECK UV > V
UVHI
, OV < V
OVLO
, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 • V
OS
AND TIMER < V
TMRL
V
OUT
1 2 3 4 56 7 8
V
ACL
V
CB
9
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
, SENSE < V
CB
AND SS < 20 • V
OS
SS
DRAIN
PWRGD
230µA + 8 • I
DRN
5.8µA
20 • V
OS
58µA
10 11
V
IN
– V
GATEH
V
DRNL
V
DRNCL
20 • (V
CB
+ V
OS
)
20 • (V
ACL
+ V
OS
)
V
GATEL
V
TMRL
V
TMRH
5.8µA
5.8µA
58µA
425212 F09
GATE
START-UP
INITIAL TIMING
Figure 9. System Power-Up Timing (All Waveforms Are Referenced to V
EE
)