Datasheet

LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
29
425212fe
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applicaTions inForMaTion
current begins to decline below V
ACL
(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point9, the SENSE voltage falls below V
CB
and TIMER
deactivates.
Large values of C
SS
can cause premature circuit breaker
time out as V
ACL
(t) may exceed the V
CB
potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large C
SS
values is SOA duration
may be exceeded during soft-start into a low impedance
load. A soft-start voltage below V
CB
will not activate the
circuit breaker TIMER.
Power Limit Circuit Breaker
Figure 19 shows the LTC4252A-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
board supply voltage, V
SUPPLY
. The D1 Zener voltage, V
Z
is set to be the same as the low supply operating voltage,
V
SUPPLY(MIN)
= 43V. If the goal is to have the high supply
operating voltage, V
SUPPLY(MAX)
= 71V giving the same
power at V
SUPPLY(MIN)
, then resistors R4 and R6 are
selected using the ratio:
R6
R4
=
V
CB
V
SUPPLY(MAX)
(16)
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
POWER
MAX
=
V
SUPPLY(MIN)
+V
SUPPLY(MAX)
( )
2
4• V
SUPPLY(MIN)
• V
SUPPLY(MAX)
•POWER
SUPPLY(MIN)
=1.064•POWER
SUPPLY(MIN)
(17)
when
V
SUPPLY
= 0.5 • (V
SUPPLY(MIN)
+ V
SUPPLY(MAX)
) = 57V.
The peak power at the fault current limit occurs at the supply
overvoltage threshold. The fault current limited power is:
POWER
FAULT
=
V
SUPPLY
R
S
• V
ACL
– V
SUPPLY
–V
Z
( )
•
R6
R4






(18)
TIMER
GATE
SENSE
SS
DRAIN
V
TMRH
V
DRNCL
V
ACL
V
CB
V
DRNL
V
GS(th)
V
IN
– V
GATEH
V
TMRL
425212 F18
PWRGD
5.8µA
58µA
58µA
TIMER
GATE
SENSE
SS
DRAIN
V
TMRH
V
DRNCL
V
CB
V
ACL
V
DRNL
V
GS(th)
V
IN
– V
GATEH
V
TMRL
PWRGD
5.8µA
58µA
58µA
12 34 567 7a 8 9 10 11
END OF INTIAL TIMING CYCLE
12 3 4 5 6 7 8 9 10 11
END OF INTIAL TIMING CYCLE
20 • V
OS
20 • (V
CB
+ V
OS
)
20 • (V
ACL
+ V
OS
)
20 • V
OS
20 • (V
CB
+ V
OS
)
20 • (V
ACL
+ V
OS
)
230µA + 8 • I
DRN
230µA + 8 • I
DRN
Figure 18. Soft-Start Timing (All Waveforms Are Referenced to V
EE
)
(18a) Without External C
SS
(18b) With External C
SS