Datasheet

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LTC4252B-1/LTC4252B-2

LTC4252C-1/LTC4252C-2

4252b12f

TYPICAL APPLICATION

FEATURES DESCRIPTION

Negative Voltage

Hot Swap Controllers

The LT C

4252 negative voltage Hot Swap

controller

allows a board to be safely inserted and removed from a

live backplane. Output current is controlled by three stages

of current limiting: a timed circuit breaker, active current

limiting and a fast feedforward path that limits peak current

under worst-case catastrophic fault conditions.

Adjustable undervoltage and overvoltage detectors dis-

connect

the load whenever the input supply exceeds the

desired operating range. The LTC4252’s supply input is

shunt regulated, allowing safe operation with very high

supply voltages. A multifunction timer delays initial start-

up and controls the circuit breaker’s response time. The

circuit breaker’s response time is accelerated by sensing

excessive MOSFET drain voltage, keeping the MOSFET

within its safe operating area (SOA). An

adjustable soft-

start circuit controls MOSFET inrush current at start-up.

The LTC4252-2 provides automatic retry after a fault. The

LTC4252C-1/LTC4252C-2 feature tight ±1% undervoltage/

overvoltage threshold accuracy. The LTC4252 is available

in either an 8-pin or 10-pin MSOP.

The LTC4252B and LTC4252C improve the ruggedness

of the shunt regulator in the LTC4252 and LTC4252A.

–48V/2.5A Hot Swap Controller

Start-Up Behavior

APPLICATIONS

Allows Safe Board Insertion and Removal from a

Live –48V Backplane

Floating Topology Permits Very High Voltage Operation

Current Limit With Circuit Breaker Timer

Fast Response Time Limits Peak Fault Current

Programmable Soft-Start Current Limit

Programmable Timer with Drain Voltage

Accelerated Response

±1% Undervoltage/Overvoltage Threshold (LTC4252C)

Improved Ruggedness Shunt Regulator

■

Adjustable Undervoltage/Overvoltage Protection

■

LTC4252B-1/LTC4252C-1: Latch Off After Fault

■

LTC4252B-2/LTC4252C-2: Automatic Retry After Fault

■

Available in 8-Pin and 10-Pin MSOP Packages

Hot Board Insertion

Electronic Circuit Breaker

–48V Distributed Power Systems

Negative Power Supply Control

Central Office Switching

High Availability Servers

ATCA

L, LT , LT C , LT M, Linear Technology and the Linear logo are registered trademarks and

Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

4252B12 TA01

–48RTN

SENSESS

TIMER GATE

PWRGD

DRAIN

LTC4252B-1

402k

32.4k

0.33µF

†

DDZ13B

68nF

18nF

–48V

0.02Ω

IRF530S

OUT

10Ω

5.1k

3× 1.8k IN SERIES

1/4W EACH

10nF

1µF

100µF

–48RTN

(SHORT PIN)

LOAD

* M0C207

**DIODES, INC

†

RECOMMENDED FOR HARSH ENVIRONMENTS

4252B12 TA01a

GATE

5V/DIV

SENSE

2.5A/DIV

PWRGD

10V/DIV

1ms/DIV

OUT

20V/DIV

Summary of content (36 pages)

PAGE 1
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 Negative Voltage Hot Swap Controllers FEATURES n n n n n n n n ■ ■ ■ ■ DESCRIPTION Allows Safe Board Insertion and Removal from a Live – 48V Backplane Floating Topology Permits Very High Voltage Operation Current Limit With Circuit Breaker Timer Fast Response Time Limits Peak Fault Current Programmable Soft-Start Current Limit Programmable Timer with Drain Voltage Accelerated Response ±1% Undervoltage/Overvoltage Threshold (LTC4252C) Improved Ruggedness Shunt
PAGE 2
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 ABSOLUTE MAXIMUM RATINGS All Voltages Referred to VEE (Note 1) Current into VIN (100µs Pulse)..............................100mA VIN, DRAIN Pin Minimum Voltage......................... – 0.3V Input/Output Pins (Except SENSE and DRAIN) Voltage........... –0.3V to 16V SENSE Pin Voltage..................................... –0.6V to 16V Current Out of SENSE Pin (20µs Pulse) ........... –200mA Current into DRAIN Pin (100µs Pulse)....................
PAGE 3
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS VZ VIN – VEE Zener Voltage IIN = 2mA l LTC4252B-1/-2 MIN TYP MAX LTC4252C-1/-2 MIN TYP MAX 11.5 11.5 13 14.5 5 13 14.5 5 UNITS V rZ VIN – VEE Zener Dynamic Impedance IIN = 2mA to 30mA IIN VIN Supply Current UV = OV = 4V, VIN = (VZ – 0.3V) ● 0.
PAGE 4
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) LTC4252B-1/-2 MIN TYP MAX LTC4252C-1/-2 MIN TYP MAX Timer On (Initial Cycle/Latchoff/ Shutdown Cooling, Sourcing), VTMR = 2V 5.8 5.
PAGE 5
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS 14.5 VZ vs Temperature 10 IIN = 2mA rZ vs Temperature 2000 IIN = 2mA 1800 9 14.0 1400 7 1200 IIN (µA) rZ (Ω) VZ (V) 13.0 6 1000 5 400 3 12.0 –55 –35 –15 200 2 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 800 600 4 12.5 VIN = (VZ – 0.3V) 1600 8 13.
PAGE 6
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS VSS vs Temperature RSS vs Temperature 2.40 2.35 2.30 45 108 40 106 35 104 2.20 2.15 100 98 5 92 2.00 –55 –35 –15 90 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 20 10 94 2.05 25 15 96 2.10 UV = OV = VSENSE = VEE IIN = 2mA VSS = 2V 30 102 ISS (mA) RSS (kΩ) 2.
PAGE 7
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS VGATEH vs Temperature 3.6 VGATEL vs Temperature 3.0 0.5 VGATEL (V) VGATEH = VIN – VGATE, IIN = 2mA (MS ONLY) 2.8 2.6 0.3 0.2 2.2 0.1 5 25 45 65 85 105 125 TEMPERATURE (°C) OV Threshold vs Temperature 6.45 –10 2.975 VUVL 2.775 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252B12 G21 ISENSE vs Temperature ISENSE vs (VSENSE – VEE) 0.01 –14 0.1 5.85 VOVL 5.45 –18 –20 –22 –24 5.25 VOV –26 5.05 –28 4.
PAGE 8
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS ITMR (Circuit Breaker, Sourcing) vs Temperature 280 ITMR (Circuit Breaker, IDRN = 50µA, Sourcing) vs Temperature 690 TIMER = 2V IDRN = 0µA 670 260 ITMR (Cooling Cycle, Sinking) vs Temperature 10 TIMER = 2V IDRN = 50µA 8 220 7 630 ITMR (A) ITMR (µA) ITMR (µA) 650 240 610 5 25 45 65 85 105 125 TEMPERATURE (°C) 8.8 TIMER ON (CIRCUIT BREAKING, IDRN = 50µA) 1 8.4 8.2 8.0 7.8 7.
PAGE 9
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS 62 220 VPWRGD = 0V (MS ONLY) 210 60 200 59 190 tSS (µs) IPGH (µA) 61 58 170 56 160 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252B12 G37 0.8 SS PIN FLOATING, VSS RAMPS FROM 0.2V TO 2V 0.7 0.6 180 57 55 –55 –35 –15 tPLLUG and tPHLOG vs Temperature tSS vs Temperature DELAY (µs) IPGH vs Temperature 150 –55 –35 –15 0.4 0.3 tPLLUG tPHLOG 0.2 0.
PAGE 10
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 PIN FUNCTIONS (MS/MS8) VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, or a circuit breaker fault timeout. GATE is actively servoed to control the fault current as measured at SENSE.
PAGE 11
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 BLOCK DIAGRAM VIN – DRAIN VIN + 2.385V 8× VEE 6.15V (5V) 1× 1× 1× VIN 58µA VEE PWRGD ** 6.15V (5.09V) VIN – 58µA VEE GATE + OV * 2.8V VIN – – + 4V 5.8µA + (–) LOGIC 230µA VIN –+ + 2.925V (3.08V) VIN – VEE – (+) UV * + 0.5V TIMER + – VIN 1V 200mV – VEE 5.8µA FCL + +– VEE VEE 22µA (28µA) + SS VOS = 10mV 95k (47.5k) 5k (2.
PAGE 12
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 OPERATION Hot Circuit Insertion Interlock Conditions When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset.
PAGE 13
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 OPERATION Two modes of operation are possible during the time the MOSFET is first turning on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to –48V and the LTC4252 will fully enhance the MOSFET.
PAGE 14
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION SHUNT REGULATOR Kelvin terminal as illustrated in Figure 3, keeping trace lengths between VIN, CIN, DIN and VEE as short as possible. A fast responding shunt regulator clamps the VIN pin to 13V (VZ). Power is derived from –48RTN by an external current limiting resistor, RIN. A 1µF decoupling capacitor, CIN filters supply transients and contributes a short delay at start-up.
PAGE 15
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION and R2 = 32.4k gives a typical operating range of 43.2V to 82.5V. The undervoltage shutdown and overvoltage recovery thresholds are then 39.2V and 74.4V. 1% divider resistors are recommended to preserve threshold accuracy. OV low-to-high (VOV) = 5.09V OV high-to-low (VOV – VOVHST) = 4.988V The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 71V when connected together as in Figure 2.
PAGE 16
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION conditions are met. A high-to-low transition in the UV comparator immediately shuts down the LTC4252, pulls the MOSFET gate low and resets the latched PWRGD high. 4) Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing. Overvoltage conditions detected by the OV comparator will also pull GATE low, thereby shutting down the load.
PAGE 17
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION NORMALIZED RESPONSE TIME (s/µF) 10 SOFT-START IDRN = 0µA Soft-start limits the inrush current profile during GATE start-up. Unduly long soft-start intervals can exceed the MOSFET’s SOA rating if powering up into an active load. If SS floats, an internal current source ramps SS from 0V to 2.2V for the LTC4252B or 0V to 1.4V for the LTC4252C in about 230µs.
PAGE 18
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (≥ 10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. GATE has two comparators: the GATE low comparator looks for < 0.5V threshold prior to initial timing or a GATE start-up cycle; the GATE high comparator looks for < 2.
PAGE 19
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 6 Trace 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4252s are used by the other cards, they respond by limiting the inrush current to a value of 100mV/RS.
PAGE 20
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Approximating a linear charging rate as IDRN drops from IDRN(MAX) to zero, the IDRN component in Equation (3) can be approximated with 0.5 • IDRN(MAX). Rearranging equation, TIMER capacitor CT is given by: CT = ( tCL(CHARGE) • 230µA + 4 •IDRN(MAX) 4V ) (13) Returning to Equation (3), the TIMER period is calculated and used in conjunction with VSUPPLY(MAX) and ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET.
PAGE 21
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION COMPENSATION CAPACITANCE CC (nF) 60 CURRENT FLOW FROM LOAD NTY100N10 CURRENT FLOW TO –48V BACKPLANE 50 SENSE RESISTOR 40 TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER 30 4252B12 F08 IRF530S IRF740 10 0 IRF3710 IRF540S 20 W 0 2000 6000 4000 MOSFET CISS (pF) 8000 4252B12 F07 Figure 7.
PAGE 22
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 3 4 56 7 8 9 10 11 GND – VEE OR (–48RTN) – (–48V) UV/OV VIN VLKO VTMRH 230µA + 8 • IDRN 5.8µA TIMER 58µA GATE 5.8µA VTMRL 58µA VGATEL 5.
PAGE 23
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 3 4 56 7 8 9 1011 GND – VEE OR (–48RTN) – (–48V) UV/OV VIN VUVHI VLKO VTMRH 5.8µA TIMER 230µA + 8 • IDRN 5.8µA VTMRL GATE SS 58µA 58µA VGATEL 5.
PAGE 24
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Undervoltage Timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO threshold. The initial timing cycle restarts, followed by a GATE start-up cycle. In Figure 11 when UV pin drops below VUVLO (time point 1), the LTC4252 shuts down with TIMER, SS and GATE all pulling low.
PAGE 25
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 3 VOVHI UV/OV 4 5 67 8 10 12 9 11 VOVLO VUVHI VTMRH 230µA + 8 • IDRN 5.8µA TIMER 5.8µA VTMRL 58µA GATE 58µA VGATEL 5.
PAGE 26
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION CB TIMES OUT 1 2 1 VTMRH 2 1 VTMRH 5.8µA TIMER 230µA + 8 • IDRN CB TIMES OUT VTMRH TIMER 230µA + 8 • IDRN TIMER GATE GATE GATE SS SS SS SENSE VACL VACL VCB VCB SENSE VOUT VOUT 2 3 230µA + 8 • IDRN 230µA + 8 • IDRN VACL VCB SENSE VOUT VDRNCL VDRNCL DRAIN DRAIN DRAIN PWRGD PWRGD PWRGD CB FAULT CB FAULT 4 5.
PAGE 27
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION SWITCH RESETS LATCHED TIMER SWITCH RELEASES SS 5.8µA 1 2 34 TIMER 67 8 9 5.8µA 58µA GATE VGATEL SS 5 VTMRH 230µA + 8 • IDRN VTMRL 58µA 5.8µA VIN – VGATEH 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL VCB SENSE VDRNCL DRAIN VDRNL PWRGD 425212B F15 GATE START-UP MOMENTARY DPST SWITCH RESET Figure 15.
PAGE 28
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Analog Current Limit and Fast Current Limit In Figure 17a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 17b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog current amplifier establishes control. If the severe fault causes VOUT to exceed VDRNCL, the DRAIN pin is clamped at VDRNCL.
PAGE 29
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION END OF INTIAL TIMING CYCLE 12 34 567 7a END OF INTIAL TIMING CYCLE 8 9 10 VTMRH 230µA + 8 • IDRN TIMER 5.8µA VTMRL 58µA GATE 11 VIN – VGATEH VGS(th) 12 3 4 5 6 TIMER 20 • (VCB + VOS) VGS(th) VCB 5.
PAGE 30
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION –48RTN RIN 3× 1.8k 1/4W EACH † –48RTN (SHORT PIN) 1 R1 392k 1% 8 10 R2 30.1k 1% –48V DIN DDZ13B** CIN 1µF VIN 9 3 CT 0.68µF C1 10nF LTC4252C-1 2 UV PWRGD 7 OV DRAIN 6 TIMER GATE 4 SS VEE SENSE CSS 68nF + R4 38.3k CL 100µF R5 100k LOAD EN D1 BZV85C43 * VOUT RD 1M Q1 IRF530S R6 27Ω RC 10Ω CC 10nF 5 RS 0.02Ω 4252B12 F19 *FMMT493 **DIODES, INC † RECOMMENDED FOR HARSH ENVIRONMENTS Figure 19.
PAGE 31
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION –48RTN + RIN 3× 1.8k 1/4W EACH † –48RTN (SHORT PIN) 1 R1 392k 1% 8 9 C1 10nF R2 30.1k 1% –48V OV UV 10 TIMER 3 CT SS 0.68µF **DIODES, INC CIN 1µF VIN LTC4252C-1 2 PWRGD 7 DRAIN GATE VEE SENSE R3 5.1k LOAD EN * VOUT RD 1M 6 R4 38.3k R 10Ω G 4 R5 27Ω Q1 IRF530S RC 10Ω CC 10nF 5 CSS 68nF *MOC207 DIN DDZ13B** CL 100µF RS 0.02Ω 4252B12 F20 † RECOMMENDED FOR HARSH ENVIRONMENTS Figure 20.
PAGE 32
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Hot Swap SECTION –48RTN RIN1 3 × 1.8k IN SERIES 1/4W EACH † R1 402k 1 7 C1 10nF 8 CT 0.33µF R2 32.4k 2 UV/OV VIN DIN1 DDZ13B** DRAIN GATE TIMER LTC4252B-1 SS VEE SENSE CSS 68nF 6 CIN 1µF RD 1M LOAD MODULE 5 3 RC1 10Ω CC1 22nF Q1 IRF530S RS 0.02Ω 4 DIODE-OR CIRCUIT FOR CHANNEL A –48V A RIN2 3 × 1.
PAGE 33
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION the current flow. The sense voltage is lifted up and causes the fast comparator of LTC4252B to trip and pull the GATE low instantly. The channel A supply short will not cause Q3 of channel B diode-OR circuit to turn off. The internal fault latches of the LTC4252B are disabled as the TIMER pin is always held low by the SS voltage when Q2 and Q3 are in analog current limit.
PAGE 34
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ± .0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.
PAGE 35
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.
PAGE 36
LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL APPLICATION –48RTN RIN 2× 5.1k IN SERIES 1/4W EACH † DIN DDZ13B** –48RTN (SHORT PIN) CL 100µF VOUT LTC4252B-1 7 R2 32.4k 1% 8 2 CT 150nF C1 10nF UV/OV DRAIN TIMER GATE SS CSS 27nF PUSH RESET VEE LOAD CIN 1µF 1 VIN R1 402k 1% + SENSE 4 6 RD 1M 5 Q1 IRF540S 3 R3 22Ω RC 10Ω CC 22nF RS 0.01Ω 4252B12 F24 –48V † **DIODES, INC RECOMMENDED FOR HARSH ENVIRONMENTS Figure 24.