LTC4259A Quad IEEE 802.3af Power over Ethernet Controller with AC Disconnect DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ The LTC®4259A is a quad –48V Hot SwapTM controller designed for use in IEEE 802.3af compliant Power Sourcing Equipment (PSE). It consists of four independent ports, each with output current limit, short-circuit protection, complete Powered Device (PD) detection and classification capability, and programmable PD disconnect using AC or DC sensing.
LTC4259A W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltages VDD to DGND .......................................... – 0.3V to 5V VEE to AGND ......................................... 0.3V to – 70V DGND to AGND (Note 2) .................................... ±1V Digital Pins SCL, SDAIN, SDAOUT, INT, AUTO, RESET SHDNn, ADn ................. DGND – 0.3V to DGND + 5V Analog Pins GATEn (Note 3) ................... VEE – 0.3V to VEE + 12V DETECTn Peak Currents (Note 4) ...
LTC4259A ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = –48V unless otherwise noted (Note 6).
LTC4259A ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = –48V unless otherwise noted (Note 6).
LTC4259A U W TYPICAL PERFOR A CE CHARACTERISTICS Power On Sequence in Auto Mode PORT 1 VDD = 3.3V VEE = –48V Powering On a 180µF Load POWER ON PORT VOLTAGE 20V/DIV GND PORT VOLTAGE 10V/DIV VDD = 3.3V VEE = –48V GND VEE DETECTION DETECTION PHASE 1 PHASE 2 CLASSIFICATION VEE GATE +14V VOLTAGE 10V/DIV VEE PORT CURRENT 0mA 500mA/DIV VEE FET ON FOLDBACK 50ms/DIV LOAD FULLY CHARGED 425mA CURRENT LIMIT 5ms/DIV 4259 G01 4259 G02 INT and SDAOUT Pull Down Voltage vs Load Current 225 450 2.
LTC4259A UW TEST TI I G PD INSERTED VPORTn 0V tDET VCLASS VGATEn VT VEE PORT TURN ON (AUTO MODE) INT tCLASS tCLSDLY 4259A F02 tDETDLY tPON Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes VLIM VCUT VSENSEn TO VEE 0V tSTART, tICUT INT 4259A F03 Figure 3. Current Limit Timing VOSCIN VOUTn VSENSEn TO VEE VMIN IACDMIN IDETECTn PD REMOVED INT tVMIN tDIS INT 4259A F04 tDIS Figure 4. DC Disconnect Timing 4259A F05 Figure 5.
LTC4259A W UW TI I G DIAGRA S SCL SDA 0 1 AD3 AD2 AD1 AD0 R/W ACK A7 0 START BY MASTER A6 A5 A4 A3 A2 A1 ACK BY SLAVE FRAME 1 SERIAL BUS ADDRESS BYTE A0 ACK D7 D6 D5 D4 D3 D2 ACK BY SLAVE D1 D0 ACK STOP BY MASTER ACK BY SLAVE FRAME 2 REGISTER ADDRESS BYTE FRAME 3 DATA BYTE 4259A F07 Figure 7.
LTC4259A U U U PI FU CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4259A is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4259A begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1µs wide from resetting the LTC4259A. Pull RESET high with ≤10k or tie to VDD.
LTC4259A U U U PI FU CTIO S AGND (Pin 21): Analog Ground. AGND should be connected to the return from the – 48V supply. AGND and DGND should be tied together. SENSE4 (Pin 22): Port 4 Current Sense Input. SENSE4 monitors the external MOSFET current via a 0.5Ω sense resistor between SENSE4 and VEE. Whenever the voltage across the sense resistor exceeds the overcurrent detection threshold VCUT, the current limit fault timer counts up.
RO RO RO RO RO 0Eh Port 3 Status 0Fh Port 4 Status 10h Power Status 11h Pin Status R/W R/W R/W R/W R/W 14h Detect/Class Enable 15h Reserved 16h Timing Config 17h Misc Config WO 1Ah Reset PB Change 4 Pwr Good Change 3 Pwr Good Mask 6 Change 2 Pwr Good Mask 5 Change 1 Pwr Good Mask 4 Class Complete Change 4 Pwr Enable Mask 3 Detect Complete BIT 3 Change 3 Pwr Enable Mask 2 Disconnect BIT 2 Change 2 Pwr Enable Mask 1 Pwr Good Event BIT 1 Change 1 Pwr Enable M
LTC4259A U U REGISTER FU CTIO S Interrupt Registers Interrupt (Address 00h): Interrupt Register, Read Only. A transition to logical 1 of any bit in this register will assert the INT pin (Pin 3) if the corresponding bit in the Int Mask register is set. Each bit is the logical OR of the corresponding bits in the Event registers. The Interrupt register is Read Only and its bits cannot be cleared directly.
LTC4259A U U REGISTER FU CTIO S disconnect enabled independently of the state of the Osc Fail bit. See AC Disconnect under Applications Information for more details. Bit 4 indicates that VEE has dropped below the VEE UVLO level (typically –28V). Bit 5 signals that the VDD supply has dropped below the VDD UVLO threshold. Bit 7 indicates that the LTC4259A die temperature has exceeded its thermal shutdown limit (see Note 5 under Electrical Characteristics).
LTC4259A U U REGISTER FU CTIO S Detect/Class Enable (Address 14h): Detection and Classification Enable, Read/Write. The lower four bits of this register enable the detection circuitry at the corresponding port if that port is in Auto or Semiauto mode. The upper four bits enable the classification circuitry at the corresponding port if that port is in Auto or Semiauto mode.
LTC4259A U U REGISTER FU CTIO S way, the condition causing the LTC4259A to pull the INT pin down must be removed before the LTC4259A will be able to pull INT down again. This can be done by reading and clearing the event registers or by writing a 1 into bit 7 of this register. Setting bit 7 releases the Interrupt pin, clears all the Event registers and clears all the bits in the Interrupt register.
LTC4259A U W U U APPLICATIO S I FOR ATIO The LTC4259A provides a complete solution for detection and powering of PD devices in an IEEE 802.3af compliant system. The LTC4259A consists of four independent ports, each with the ability to detect, classify, and provide isolated –48V power to a PD device connected to it. The LTC4259A senses removal of a PD with IEEE 802.3af compliant AC or DC methods and turns off –48V power when the PD is removed.
LTC4259A U W U U APPLICATIO S I FOR ATIO The LTC4259A checks for the signature resistance by forcing two test currents on the port (via the DETECTn pins) in sequence and measuring the resulting voltages. It then subtracts the two V-I points to determine the resistive slope while removing voltage offset caused by any series diodes or current offset caused by leakage at the port (see Figure 13).
LTC4259A U W U U APPLICATIO S I FOR ATIO measures the port voltage through the DETECTn pin. Note that class 4 is presently specified by the IEEE as reserved for future use. Figure 14 shows a PD load line, starting with the shallow slope of the 25k signature resistor below 10V, then drawing the classification current (in this case, class 3) between 14.5V and 20.5V. The LTC4259A’s load line for classification is also shown in Figure 14. It has low impedance until current limit at 65mA (typ).
LTC4259A U W U U APPLICATIO S I FOR ATIO Dual-Level Current Limit A PD is permitted to draw up to 15.4W continuously and up to 400mA for 50ms. The LTC4259A has two corresponding current limit thresholds, ICUT (375mA typ) and ILIM (425mA typ). These are given by the equations: ICUT = VCUT/RS, ILIM = VLIM/RS RS is the sense resistor and should be 0.5Ω for IEEE 802.3af compliance.
LTC4259A U W U U APPLICATIO S I FOR ATIO Foldback Choosing External MOSFETs Foldback is designed to limit power dissipation in the MOSFET during power-up and momentary short-circuit conditions. At low port output voltages, the voltage across the MOSFET is high, and power dissipation will be large if significant current is flowing. Foldback monitors the port output voltage and reduces the VLIM current limit level linearly from its full value (212.
LTC4259A U W U U APPLICATIO S I FOR ATIO noncompliant PD with only a few ohms of resistance. With foldback, the MOSFET sees a maximum of 18W for the duration of tSTART. The LTC4259A’s duty cycle protection enforces 15 times longer off time than on time, preventing successive attempts to power a defective PD from damaging the MOSFET. System software can enforce even longer wait times.
LTC4259A U W U U APPLICATIO S I FOR ATIO the minimum specified current. The disconnect timer counts up whenever port current is below 7.5mA (typ). If the tDIS timer runs out, the corresponding port will be turned off and the disconnect bit in the fault register will be set. If the undercurrent condition goes away before the tDIS timer runs out, the timer will reset. The timer will start counting from the beginning if the undercurrent condition occurs again.
LTC4259A U W U U APPLICATIO S I FOR ATIO values of CDET, RDET and CPSE is discouraged. Contact the LTC Applications department for additional support. When choosing CDET and CPSE, carefully consider voltage derating of the capacitors. Capacitors built around an X7R dielectric will have about 60% of the specified capacitance at their rated voltage. Operated at half their rated voltage, X7R capacitors exhibit more than 80% of their specified capacitance.
LTC4259A U W U U APPLICATIO S I FOR ATIO OSCIN Input and Oscillator Requirements AC disconnect depends on an external oscillator source applied to the OSCIN pin. The LTC4259A measures port impedance by applying an amplified version of the OSCIN signal to the port’s DETECT pin (see Figure 18). The oscillator should be well-controlled because errors in this signal become errors in the measured port impedance.
LTC4259A U W U U APPLICATIO S I FOR ATIO lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. If the SDA and SCL pull-ups are absent, not connected to the same positive supply as the LTC4259A’s VDD pin, or are not activated when the power is applied to the LTC4259A, it is possible for the LTC4259A to see a START condition on the I2C bus.
LTC4259A U W U U APPLICATIO S I FOR ATIO 0.1µF VDD LTC4259A INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND BYP 0.1µF 0.1µF VDD CPU U1 SCL 2k 200Ω 0100000 0.1µF VDD LTC4259A INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND BYP 2k U2 200Ω I2C ADDRESS 0100001 0.1µF SDA 0.1µF HCPL-063L TO CONTROLLER U3 200Ω 200Ω SMBALERT 0.1µF 0.1µF GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L VDD LTC4259A INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND BYP 0.
LTC4259A U W U U APPLICATIO S I FOR ATIO clock pulse. The slave must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. When the master is reading from a slave device, it is the master’s responsibility to acknowledge receipt of the data byte in the bit that follows unless the transaction is complete. In that case the master will decline to acknowledge and issue the STOP condition to terminate the communication.
LTC4259A U W U U APPLICATIO S I FOR ATIO System Software Strategy Control of the LTC4259A hinges on one decision, the LTC4259A’s operating mode. The three choices are described under Operating Modes. In Auto mode the LTC4259A can operate autonomously without direction from a host controller. Because LTC4259As running in Auto mode will power every valid PD connected to them, the PSE must have 15.4W/port available.
LTC4259A U W U U APPLICATIO S I FOR ATIO B1100 100µH ISOLATED GND 910k + 1µF 100V 510Ω 4.7µH 3.32k 1% Si2328DS + 47µF 10V 10µF 16V 8 VIN 7 ISOLATED GND 6 DRV GATE 5 SENSE LT1619 FB S/S GND VC 1 4 3 FMMT593 FMMT593 2 0.100Ω 1% 1W 47k 1.24k 1% 100k 100pF 4700pF VEE ISOLATED –48V 47µF 10V 100Ω Si2328DS CMPZ4702B + VDD 3.3V 300mA 10Ω 4259A F21 Figure 21. –48V to 3.
LTC4259A U W U U APPLICATIO S I FOR ATIO a current loop can form. In such a loop, common mode current flows in one port and out the other, and the choke will not prevent this because the sum of the currents is zero. Another way to view this interaction between the paired ports is that the choke acts as a transformer coupling the ports’ common modes together. In nonpowered Ethernet, common mode current results from nonidealities like ground loops; it is not part of normal operation.
LTC4259A U W U U APPLICATIO S I FOR ATIO cases the port voltage must always stay between –44V and –57V. In addition, the 802.3af specification places specific ripple, noise and load regulation requirements on the PSE. Among other things, disturbances on either VDD or VEE can adversely affect detection, classification and the AC disconnection sensing. Proper bypassing and stability of the VDD and VEE supplies is important.
LTC4259A U PACKAGE DESCRIPTIO GW Package 36-Lead Plastic SSOP (Wide .300 Inch) (Reference LTC DWG # 05-08-1642) 1.143 ±0.127 10.668 MIN 15.290 – 15.544* (.602 – .612) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.416 – 7.747 10.160 – 10.414 (.400 – .410) 0.520 ±0.0635 0.800 TYP RECOMMENDED SOLDER PAD LAYOUT 7.417 – 7.595** (.292 – .299) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.286 – 2.387 (.090 – .094) 2.463 – 2.641 (.097 – .104) 0.254 – 0.406 × 45° (.010 – .
LTC4259A U TYPICAL APPLICATIO 2VP-P, 100Hz 1.2V OFFSET OSCILLATOR ISOLATED 3.3V 1k ISOLATED GND 0.1µF 0.1µF 100V X7R OSCIN DGND AGND 2k U2 200Ω VDD BYP DETECT U1 SCL 2k 200Ω VEE SENSE GATE OUT 0.1µF TO CONTROLLER RS 0.5Ω SDA HCPL-063L –48V ISOLATED U3 0.1µF 100V X7R RDET 1k SCL 1/4 SDAIN LTC4259A SDAOUT INT VDD CPU 1µF DDET CMPD3003 L1 CDET 0.47µF 100V X7R DTSS 58V SMAJ58A 10k Q1 IRFM120A DAC S1B RJ45 CONNECTOR 1/2 PULSE H2009 200Ω 0.01µF 200V 75Ω 75Ω 0.01µF 200V 0.
