LTC4260 Positive High Voltage Hot Swap Controller with I2C Compatible Monitoring Description Features n n n n n n n n n n Allows Safe Board Insertion into Live Backplane 8-Bit ADC Monitors Current and Voltage I2C™/SMBus Interface Wide Operating Voltage Range: 8.
LTC4260 Absolute Maximum Ratings (Notes 1, 2) Supply Voltages (VDD)..............................– 0.3V to 100V Input Voltages SENSE...............................VDD – 10V or –0.3V to VDD SOURCE............................. GATE – 5V to GATE + 0.3V BD_PRST, FB, ON, OV, UV....................... –0.3V to 12V ADR0-ADR2, TIMER, ADIN.........–0.3V to INTVCC + 0.3V SCL, SDAI............................................. –0.3V to 6.5V Output Voltages GPIO..................................................... –0.
LTC4260 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS General VDD Input Supply Range l IDD Input Supply Current l 8.5 VDD(UVL) VDD Supply Undervoltage Lockout VDD Falling l 7 INTVCC(UVL) VCC Supply Undervoltage Lockout INTVCC Falling l 3.
LTC4260 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VTIMER(H) TIMER Pin High Threshold VTIMER Rising l 1.2 1.235 1.28 V VTIMER(L) TIMER Pin Low Threshold VTIMER Falling l 0.1 0.2 0.
LTC4260 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN Operates with fSCL ≤ fSCL(MAX) 400 TYP MAX UNITS I2C Interface Timing (Note 4) fSCL(MAX) Maximum SCL Clock Frequency tBUF(MIN) Minimum Bus Free Time Between Stop/Start Condition tSU,STA(MIN) kHz 0.12 1.
LTC4260 Typical Performance Characteristics 3.0 TA = 25°C, VDD = 48V unless otherwise noted. UV Low-High Threshold vs Temperature INTVCC vs ILOAD IDD vs VDD 6 3.54 VDD = 48V 2.0 VDD = 12V 4 25°C INTVCC (V) IDD (mA) 85°C –40°C UV LOW-HIGH THRESHOLD (V) 5 2.5 3 2 1.5 1.0 0 20 60 40 VDD (V) 80 MAX ILOAD = 4.
LTC4260 Typical Performance Characteristics IGATE Pull Up vs Temperature Gate Drive vs IGATE 16 –20 –15 –10 –50 –25 0 25 50 TEMPERATURE (°C) 75 14 VDD = 80V 12 VDD = 48V 10 8 6 VDD = 12V 4 2 0 100 GATE DRIVE (VGATE – VSOURCE) (V) 16 GATE DRIVE (VGATE – VSOURCE) (V) IGATE PULL UP (µA) –25 0 –10 –5 10 8 6 14 13 12 10 8 6 4 2 75 0 100 0 10 20 40 30 IGPIO (mA) 50 –2 60 64 128 192 ADC DNL (LSB) 0.25 ADC INL (LSB) 0.25 0 –0.25 –0.
LTC4260 Pin Functions ADIN: ADC Input. A voltage between 0V and 2.56V applied to this pin can be measured by the onboard ADC. Tie to ground if unused. ADR0 to ADR2: Serial Bus Address Inputs. Tying these pins to ground, open or INTVCC configures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open-drain logic output that can be pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the ALERT register.
LTC4260 Pin Functions SDAO: Serial Bus Data Output. Open-drain output used for sending data back to the master controller or acknowledging a write operation. Normally tied to SDAI to form the SDA line. An external pull-up resistor or current source is required. SENSE: Current Sense Input. Connect this pin to the output of the current sense resistor.
LTC4260 functional Diagram UH ONLY VDD FB VDDK SENSE 18Ω 3.5V INTERNAL POWER + UV UV 20mV TO 50mV UVS – +– + GATE – CHARGE PUMP AND GATE DRIVER CS + 16.5V SOURCE FOLDBACK OV 2V + GN/UH ONLY OV 3.5V + – PWRGD PG + RST FET ON – 3.5V 1.235V – OVS RESET – INTVCC 10µA GP LOGIC 1.235V + BP BD_PRST – BOARD PRESENT – INTVCC – + ON 1.235V 100µA TIMER ONS 2µA + – VDD TM2 VDD UVLO1 7.45V – 1.235V – 1.8V + 0.2V TM1 ON GPIO + INTVCC 5.
LTC4260 timing Diagram SDAI/SDAO tSU, DAT tSU, STA tHD, DATO, tHD, DATI tSP tHD, STA tSP tBUF tSU, STO 4260 TD01 SCL tHD, STA START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Operation The Functional Diagram displays the main functional areas of this device. The LTC4260 is designed to turn a board’s supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane.
LTC4260 Applications Information The typical LTC4260 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. The device measures card voltages and currents and records past and present fault conditions. The system queries each LTC4260 over the I2C periodically and reads the stored information. control registers are set or cleared as described in the register section.
LTC4260 Applications Information VDD + 13V GATE SLOPE = 18µA/C1 VOUT VDD t1 t2 4260 F02 Figure 2. Supply Turn-On As the SOURCE voltage rises, so will the FB pin which is monitoring it. If the voltage across the current sense resistor RS gets too high, the inrush current will then be limited by the internal current limit circuitry. Once the FB pin crosses its 3.5V threshold, the GPIO pin, in its default configuration, will cease to pull low and indicate that the power is now good.
LTC4260 Applications Information undervoltage autoretry has been disabled by clearing bit A1. When power is applied to the device, if UV is below its 3.12V threshold after INTVCC crosses its 4.5V undervoltage lockout threshold, an undervoltage fault will be logged in the fault register. VOUT 50V/DIV IOUT 5A/DIV ∆VGATE 10V/DIV Board Present Change of State TIMER 2V/DIV 4260 F03 100µs/DIV Figure 3.
LTC4260 Applications Information OUT 23 LTC4260 SOURCE 10µA BD_PRST 14 + LOAD CBD_PRST – Resetting Faults 1.235V GND 6 4260 F04 MOTHERBOARD Once the ALERT signal has been released for one fault, it will not be pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated FAULT register bit has been cleared.
LTC4260 Applications Information Gate Pin Voltage A curve of gate drive vs VDD is shown in the Typical Performance curves. At the minimum input supply voltage of 8.5V, the minimum gate drive voltage is 4.5V. When the input supply voltage is higher than 20V, the gate drive is at least 10V and a regular N-FET can be used. In applications over a 8.5V to 20V range, a logic level N-FET must be used to maintain adequate gate enhancement. The GATE pin is clamped at a typical value of 15V above the SOURCE pin.
LTC4260 Applications Information The SOA (safe operating area) curves of candidate FETs must be evaluated to ensure that the heat capacity of the package can stand 24W for 16ms. The SOA curves of the Fairchild FDB3632 provide for 1A at 50V (50W) for 10ms, satisfying the requirement. The inrush current is set to 1A using C1: C1= CL IGATE(UP) 18µA = 0.33mF = 5.9nF IINRUSH 1A Default values of R5 = 10Ω and R6 = 100k are chosen as discussed previously.
LTC4260 Applications Information Digital Interface Acknowledge The LTC4260 communicates with a bus master using a 2‑wire interface compatible with the I2C bus and the SMBus, an I2C extension for low power devices. The acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse.
LTC4260 Applications Information R/W bit now set to one. The LTC4260 acknowledges and sends the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command (Figure 12), the LTC4260 will repeat the requested register as the second data byte. Note that the Register Address pointer is not cleared at the end of the transaction.
LTC4260 Applications Information S ADDRESS W A 1 0 a4:a0 0 0 A DATA A P COMMAND X X X X X b2:b0 FROM MASTER TO SLAVE 0 b7:b0 0 A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION FROM SLAVE TO MASTER 4260 F07 Figure 7. LTC4260 Serial Bus SDA Write Byte Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND A DATA A DATA X X X X X b2:b0 0 b7:b0 0 XXXXXXXX A P 0 4260 F08 Figure 8.
LTC4260 Applications Information Table 1.
LTC4260 Applications Information Table 2.
LTC4260 Applications Information Table 4. ALERT Register B (01h)—Read/Write BIT NAME OPERATION B7 Reserved Not Used B6 GPIO Output Output Data Bit to GPIO Pin When Configured as Output.
LTC4260 Applications Information Table 6.
LTC4260 Applications Information RS 0.003Ω VIN 12V Q1 Si7880DP R1 5.76k 1% CF 0.1µF 25V R5 10Ω R6 100k R3 2.05k 5 1% 10 9 8 11 7 4 2 1 24 23 UV VDD SENSE GATE SOURCE FB OV SDAO ADIN SDAI LTC4260GN GPIO SCL BD_PRST ALERT ON TIMER INTVCC ADR0 ADR1 ADR2 GND 19 15 CL 1000µF 17 R4 100k 18 13 20 14 12 CT 0.68µF 6 NC C3 0.1µF GND 16 + R8 2.94k 1% C1 22nF R2 1k 1% SDA SCL ALERT R7 6.65k 1% 4260 F12 BACKPLANE PLUG-IN CARD Figure 12. 12A, 12V Card Resident Application RS 0.
LTC4260 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .033 (0.838) REF .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ±.0015 2 3 4 5 6 7 8 9 10 11 12 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ±.004 × 45° (0.38 ±0.
LTC4260 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. SW Package 24-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP N 24 23 22 21 .598 – .614 (15.190 – 15.600) NOTE 4 20 19 18 17 16 15 14 13 N .325 ±.005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) NOTE: 1.
LTC4260 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.50 REF (4 SIDES) 3.45 ± 0.05 3.45 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ± 0.05 R = 0.05 TYP 0.00 – 0.05 R = 0.
LTC4260 Revision History (Revision history begins at Rev B) REV DATE DESCRIPTION B 1/12 Revised Conditions and Min value for IGATE(FST) PAGE NUMBER 3 Corrected typographical error in Layout Considerations section 17 C 5/13 Removed erroneous temperature dot from ΔVGPIO(TH) 3 Corrected Full Scale Voltage of SOURCE to 102V 4 Corrected ILOAD to IGPIO in G13 7 Illustrated a 16.
LTC4260 Typical Application 3A, 48V Backplane Resident Application with Insertion Activated Turn-On VIN 48V 0.01Ω FDB3632 VOUT 48V SMBT70A 43.5k 49.9k 10Ω 0.1µF 100k 3.57k 6.8nF 100k 1.74k 2.67k UV VDD SENSE GATE SOURCE OV FB ON GPIO SDAI BD_PRST LTC4260 SDA0 ADIN SCL TIMER ALERT INTVCC ADR0 ADR1 ADR2 GND LOAD 1µF 68nF NC 4260 TA03 0.
