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LTC4266

4266fe

For more information www.linear.com/LTC4266

High Power PSE Switches/Routers

High Power PSE Midspans

ApplicAtions

FeAtures Description

Quad IEEE 802.3at Power

over Ethernet Controller

The LT C

4266 is a quad PSE controller designed for use

in IEEE 802.3 Type 1 and Type 2 (high power) compliant

Power over Ethernet systems. External power MOSFETs

enhance system reliability and minimize channel resis-

tance, cutting power dissipation and eliminating the need

for heatsinks even at Type 2 power levels. External power

components also allow use at very high power levels while

remaining otherwise compatible with the IEEE standard.

80V-rated port pins provide robust protection against

external faults.

The LTC4266 includes advanced power management

features, including current and voltage readback and pro-

grammable I

CUT

and I

LIM

thresholds. Available C libraries

simplify power-management software development; an

optional AUTO pin mode provides fully IEEE-compliant

standalone operation with no software required. Proprietary

4-point PD detection circuitry minimizes false PD detec-

tion while supporting legacy phone operation. Midspan

operation is supported with built-in 2-event classification

and backoff timing. Host communication is via a 1MHz

C serial interface.

The LTC4266 is available in a 5mm × 7mm QFN package

that significantly reduces board space compared with

competing solutions. A legacy-compatible 36-pin SSOP

package is also available.

Four Independent PSE Channels

Compliant with IEEE 802.3at Type 1 and 2

0.34Ω Total Channel Resistance

130mW/Port at 600mA

Advanced Power Management

8-Bit Programmable Current Limit (I

LIM

)

7-Bit Programmable Overload Currents (I

CUT

)

Fast Shutdown of Preselected Ports

14.5-Bit Port Current/Voltage Monitoring

2-Event Classification

Very High Reliability 4-Point PD Detection:

2-Point Forced Voltage

2-Point Forced Current

High Capacitance Legacy Device Detection

LTC4259A-1 and LTC4258 Pin and SW Compatible

1MHz I

C Compatible Serial Control Interface

Midspan Backoff Timer

Supports Proprietary Power Levels Above 25W

Available in 38-Pin 5mm × 7mm QFN and 36-Pin

SSOP Packages

typicAl ApplicAtion

Complete 4-Port Ethernet High Power Source

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

4266 TA01

SCL

SDAIN

SDAOUT

AD0

AD1

AD2

AD3

AGND V

SENSE1

–50V

1µFSMAJ58A

GATE1 OUT1 OUT2 OUT3SENSE2 GATE2 SENSE3 GATE3 SENSE4 GATE4 OUT4

PORT1

–50V

0.22µF 100V

×4

S1B

×4

S1B

×4

PORT2

PORT3

PORT4

DGND

INT SHDN1 SHDN2 AUTO MSD RESETSHDN3 SHDN4 MID

0.1µF

3.3V

LTC4266

Summary of content (30 pages)

PAGE 1
LTC4266 Quad IEEE 802.3at Power over Ethernet Controller Description Features n n n n n n n n n n n Four Independent PSE Channels Compliant with IEEE 802.3at Type 1 and 2 0.34Ω Total Channel Resistance 130mW/Port at 600mA Advanced Power Management 8-Bit Programmable Current Limit (ILIM) 7-Bit Programmable Overload Currents (ICUT) Fast Shutdown of Preselected Ports 14.
PAGE 2
LTC4266 Absolute Maximum Ratings Supply Voltages (Note 1) AGND – VEE............................................ –0.3V to 80V DGND – VEE............................................ –0.3V to 80V VDD – DGND.......................................... –0.3V to 5.5V Digital Pins SCL, SDAIN, SDAOUT, INT, SHDNn, MSD, ADn, RESET, AUTO, MID............ DGND –0.3V to VDD + 0.3V Analog Pins GATEn, SENSEn, OUTn........... VEE –0.3V to VEE + 80V Operating Temperature Range LTC4266C.......................................
PAGE 3
LTC4266 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS Main PoE Supply Voltage AGND – VEE For IEEE Type 1 Complaint Output For IEEE Type 2 Complaint Output Undervoltage Lock-out Level VDD VDD Supply Voltage VDD – DGND Undervoltage Lock-out MIN l l 45 51 l 20 l 3.
PAGE 4
LTC4266 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Overcurrent Sense Voltage VSENSEn – VEE, icut12 = icut34 = hpen = 00h hpen = 0Fh, cutn[5:0] ≥ 4 (Note 12) cutrng = 0 cutrng = 1 l 180 188 196 mV l l 9 4.5 9.38 4.69 9.75 4.
PAGE 5
LTC4266 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 6
LTC4266 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 7
LTC4266 Typical Performance Characteristics Power On Sequence in AUTO Pin Mode 10 0 GND PORT VOLTAGE (V) FORCED VOLTAGE DETECTION –40 PORT 1 VDD = 3.3V VEE = –54V –50 –60 VDD = 3.3V VEE = –54V PORT VOLTAGE 20V/DIV –10 –30 GND GND FORCED CURRENT DETECTION –20 802.3af Classification in AUTO Pin Mode Powering Up into a 180µF Load LOAD FULLY CHARGED VEE PORT CURRENT 200 mA/DIV 802.3af CLASSIFICATION POWER ON FOLDBACK 0mA GATE VOLTAGE 10V/DIV VEE VEE –70 –18.
PAGE 8
LTC4266 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af ILIM Threshold vs Temperature 163 162 429 426 423 105.75 105.00 –40 0 420 120 40 80 TEMPERATURE (°C) 652 VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 47h = E2h PORT 1 648 161 644 160 640 159 636 158 –40 0 40 80 TEMPERATURE (°C) 4266 G10 DC Disconnect Threshold vs Temperature 384 2.0000 381 1.9375 378 93.75 375 93.00 –40 0 372 120 80 40 TEMPERATURE (°C) 8.00 VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 47h = E2h PORT 1 7.75 1.
PAGE 9
LTC4266 TYPICAL PERFORMANCE CHARACTERISTICS ADC Noise Histogram Current Readback in Slow Mode ADC INTEGRAL NONLINEARITY (LSBs) 250 BIN COUNT 200 150 100 50 6139 600 1.0 VSENSEn – VEE = 110.4mV 0 6141 6143 ADC OUTPUT 6145 6147 500 400 0 200 100 –1.0 BIN COUNT 400 300 200 –0.5 100 50 60 0 8533 8532 4266 G20 8534 8535 ADC OUTPUT 8536 0 –0.5 –1.0 0 10 20 40 30 PORT VOLTAGE (V) GND 2 60 4266 G22 VDD = 3.3V VEE = –54V PORT VOLTAGE 20V/DIV 2.
PAGE 10
LTC4266 Test Timing Diagrams tDET CLASSIFICATION FORCED-CURRENT VPORTn FORCEDVOLTAGE 0V tME1 tME2 VOC VMARK 15.5V VCLASS 20.5V tCLE1 tCLE2 PD CONNECTED tCLE3 tPON tDETDLY VEE INT 4266 F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes VLIM VCUT VSENSEn TO VEE 0V VSENSEn TO VEE VMIN tSTART, tICUT INT INT tMPS tDIS 4266 F03 4266 F02 Figure 3. DC Disconnect Timing Figure 2.
PAGE 11
LTC4266 I2C Timing Diagrams SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 START BY MASTER A6 A5 A4 A3 A2 FRAME 1 SERIAL BUS ADDRESS BYTE A0 ACK D7 A1 ACK BY SLAVE D6 D5 D4 D3 D2 ACK BY SLAVE D1 D0 ACK STOP BY MASTER ACK BY SLAVE FRAME 2 REGISTER ADDRESS BYTE FRAME 3 DATA BYTE 4266 F06 Figure 6.
PAGE 12
LTC4266 Pin Functions RESET: Chip Reset, Active Low. When the RESET pin is low, the LTC4266 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4266 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1µs wide from resetting the LTC4266. Internally pulled up to VDD. MID: Midspan Mode Input.
PAGE 13
LTC4266 PIN FUNCTIONS GATE4: Port 4 Gate Drive. GATE4 should be connected to the gate of the external MOSFET for port 4. When the MOSFET is turned on, the gate voltage is driven to 12V (typ) above VEE. During a current limit condition, the voltage at GATE4 will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE4 is pulled down, turning the MOSFET off and recording a tCUT or tSTART event. If the port is unused, float the GATE4 pin.
PAGE 14
LTC4266 Operation Overview Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W. This initial spec was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.
PAGE 15
LTC4266 Operation more power that the PSE has available. The classification step is optional; if a PSE chooses not to classify a PD, it must assume that the PD is a 13W (full 802.3af power) device. compatible) devices can be substituted with the LTC4266 without software or PCB layout changes; only minor BOM changes are required to implement a fully compliant 802.3at design. New in 802.
PAGE 16
LTC4266 Applications Information Operating Modes Reset and the AUTO/MID Pins The LTC4266 includes four independent ports, each of which can operate in one of four modes: manual, semiauto, AUTO pin or shutdown. The initial LTC4266 configuration depends on the state of the AUTO and MID pins during reset. Reset occurs at power-up, or whenever the RESET pin is pulled low or the global Reset All bit is set.
PAGE 17
LTC4266 APPLICATIONS INFORMATION PD 10k 20k 150Ω (NIC) PSE 15k 30k 23.75k 26.25k 19k 26.5k 33k 275 4266 F11 Figure 11. IEEE 802.3af Signature Resistance Ranges the must-accept and must-reject ranges. In particular, the PSE must reject standard computer network ports, many of which have 150Ω common mode termination resistors that will be damaged if power is applied to them (the black region at the left of Figure 11).
PAGE 18
LTC4266 APPLICATIONS INFORMATION Detection of Legacy PDs Proprietary PDs that predate the original IEEE 802.3af standard are commonly referred to today as legacy devices. One type of legacy PD uses a large common mode capacitance (>10μF) as the detection signature. Note that PDs in this range of capacitance are defined as invalid, so a PSE that detects legacy PDs is technically noncompliant with the IEEE spec. The LTC4266 can be configured to detect this type of legacy PD.
PAGE 19
LTC4266 APPLICATIONS INFORMATION The second 802.3at classification method, known as 2-event classification or ping-pong, is fully supported by the LTC4266. A Type 2 PD that is requesting more than 13W will indicate Class 4 during normal 802.3af classification. If the LTC4266 sees Class 4, it forces the port to a specified lower voltage (called the mark voltage, typically 9V), pauses briefly, and then re-runs classification to verify the Class 4 reading (Figure 1).
PAGE 20
LTC4266 APPLICATIONS INFORMATION 1.0 09 372 8B 425 00 478 8E 531 92 584 CB 638 10 90 744 D2 9A 850 40 C0 956 4A CA 1063 50 D0 1169 5A DA 1275 60 E0 1488 52 25 sA m 0.3 802.3af FOLDBACK 0.2 0.1 0.0 89 49 1700 40 1913 4A 2125 50 2338 5A 2550 60 2975 52 60 4266 F14 1.0 25 °C 0.9 T 75 m sA 0.8 A 0.7 T sA SO 8A 10 30 40 50 20 PD VOLTAGE (V) AT VPSE = 58V Figure 14.
PAGE 21
LTC4266 APPLICATIONS INFORMATION The LTC4266 will support current levels well beyond the maximum values in the 802.3at specification. The shaded areas in Table 5 indicate settings that may require a larger external MOSFET, additional heat sinking, or a reduced tLIM setting. MOSFET Fault Detection LTC4266 PSE ports are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged.
PAGE 22
LTC4266 APPLICATIONS INFORMATION supply. If a port is turned off via MSD, the corresponding detection and classification enable bits are cleared, so the port will remain off until the host explicitly re-enables detection. Serial Digital Interface Overview The LTC4266 communicates with the host using a standard SMBus/I2C 2-wire interface. The LTC4266 is a slave-only device, and communicates with the host master using the standard SMBus protocols. Interrupts are signaled to the host via the INT pin.
PAGE 23
LTC4266 APPLICATIONS INFORMATION L3 100µH SUMIDA CDRH5D28-101NC C77 0.22µF 100V C76 10µF 63V + C78 0.22µF 100V R60 10Ω C74 100µF 6.3V C75 10µF 16V R53 4.7k 1% 5 VCC 1 R58 10Ω VEE R51 4.7k 1% R54 56k C79 2200pF ITH/RUN L4 10µH SUMIDA CDRH4D28-100NC D28 B1100 C73 10µF 6.3V R52 3.32k 1% Q13 FMMT723 NGATE 6 3.3V AT 400mA Q14 FMMT723 Q15 FDC2512 LTC3803 3 VFB SENSE 4 GND 2 R57 1k R55 806Ω 1% R59 0.100Ω 1%, 1W R56 47.5k 1% 4266 F17 Figure 17.
PAGE 24
LTC4266 APPLICATIONS INFORMATION 0.1µF 0.1µF I2C ADDRESS VDD LTC4266 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 0100000 VDD LTC4266 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 0100001 VDD LTC4266 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 0100010 0.1µF VDD CPU 2k U2 200Ω U1 SCL 2k 200Ω SDA 0.1µF HCPL-063L TO CONTROLLER U3 200Ω 200Ω SMBALERT 0.1µF 0.1µF GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L HCPL-063L 0.1µF ISOLATED 3.
PAGE 25
LTC4266 APPLICATIONS INFORMATION Four commonly available 1Ω resistors (0402 or larger package size) can be used in parallel in place of a single 0.25Ω resistor. In order to meet the ICUT and ILIM accuracy required by the IEEE specification, the sense resistors should have ±1% tolerance or better, and no more than ±200ppm/°C temperature coefficient. Output Cap Each port requires a 0.22μF cap across its outputs to keep the LTC4266 stable while in current limit during startup or overload.
PAGE 26
LTC4266 APPLICATIONS INFORMATION a perfect Kelvin connection because all four ports controlled by the LTC4266 share the same sense trace, and because the current through the trace (IEE) is not zero. However, as the equation shows, the remaining error is a small offset term. Figure 20 shows two LTC4266 chips controlling eight ports (A though H). The ports are separated into two groups of four; each has its own trace on the top PCB layer that connects to the VEE plane with a via.
PAGE 27
LTC4266 APPLICATIONS INFORMATION EDGE OF VEE PLANE (ON SOME INNER LAYER) KELVIN SENSE TRACE CONNECTS U1 TO VEE THROUGH THE VIAS ON THE RIGHT PORT A RSENSE PORT B RSENSE PIN 1 FOUR LARGE VIAS TO VEE PLANE HOLE IN VEE PLANE U1 PORT C RSENSE THE PADDLE IS CONNECTED TO VEE PINS VIAS TO SOURCE PIN OF THE PORT D MOSFET LOCATED ON THE OPPOSITE SIDE OF THE BOARD PORT D RSENSE 4266 F21 Figure 21. Good PCB Layout Example Package Description Please refer to http://www.linear.
PAGE 28
LTC4266 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 ± 0.05 5.50 ± 0.05 5.15 ± 0.05 4.10 ± 0.05 3.00 REF 3.15 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 5.5 REF 6.10 ± 0.05 7.50 ± 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 0.75 ± 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 3.
PAGE 29
LTC4266 Revision History (Revision history begins at Rev B) REV DATE DESCRIPTION B 3/11 Revised AGND and DGND pin references throughout data sheet. C 8/11 PAGE NUMBER Revised auto mode to AUTO pin mode throughout data sheet. 1 to 26 Added text to Operating Modes and made minor text edits throughout Applications Information section. 19 to 26 Changed –48 Supply Voltage to Main PoE Supply Voltage. Changed Gate Typical voltage to 12V.
PAGE 30
LTC4266 Typical Application ISOLATED 3.3V ISOLATED GND 0.1µF DGND AGND 2k U2 200Ω VDD CPU FB1 SCL 1/4 SDAIN LTC4266 SDAOUT INT U1 SCL VEE 2k 200Ω TO CONTROLLER 0.22µF 100V X7R VDD 1µF 100V X7R SENSE GATE OUT FB2 S1B RS 0.25Ω SDA Q1 HCPL-063L U3 SMAJ58A 200Ω –48V ISOLATED S1B RJ45 CONNECTOR T1 • 200Ω INTERRUPT • • • • 0.01µF 200V 75Ω 0.01µF 200V 75Ω 75Ω 75Ω 1 2 3 4 5 6 7 8 • PHY 0.