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LTC4270/LTC4271

42701fc

PoE PSE Switches/Routers

PoE PSE Midspans

APPLICATIONS

TYPICAL APPLICATION

FEATURES

DESCRIPTION

12-Port PoE/PoE

/LTPoE

PSE Controller

The LT C

4270/LTC4271 chipset is a 12-port power sourc-

ing equipment (PSE) controller designed for use in IEEE

802.3at Type 1 and Type 2 (high power) compliant Power

over Ethernet (PoE) systems. Transformer-isolated com-

munication protocol replaces expensive opto-couplers

and complex isolated 3.3V supply resulting in significant

BOM cost savings. The LTC4270/LTC4271 chipset delivers

lowest-in-industry heat dissipation by utilizing low-R

DS(ON)

external MOSFETs and 0.25Ω sense resistors.

Advanced power management features include per-port 12-

bit current monitoring ADCs, DAC-programmable current

limit, and versatile fast shut-down of preselected ports.

Advanced power management host software is available

under a no-cost license. PD discovery uses a proprietary

dual-mode 4-point detection mechanism ensuring excel-

lent immunity from false

PD detection. Midspan PSEs

are supported with 2-event classification and a 2 second

backoff timer. The LTC4270/LTC4271 includes an I

serial interface operable up to 1MHz.

The LTC4270/LTC4271 is available in multiple power

grades allowing delivered PD power up to 90W.

12 Independent PSE Channels

Compliant with IEEE 802.3at Type 1 and 2

Chipset Provides Electrical Isolation

Reduced BOM Cost

Eliminates up to 6 High Speed Opto-Couplers

Eliminates Isolated 3.3V Power Supply

Low Power Dissipation

0.25Ω Sense Resistance Per Channel

Very High Reliability 4-Point PD Detection

2-Point Forced Voltage

2-Point Forced Current

and V

PORT

Monitoring

1 Second Rolling I

PORT

Averaging

Supports 2-Pair and 4-Pair Output Power

1MHz I

C Compatible Serial Control Interface

Available In Three Power Grades

A-Grade – LTPoE

™

38.7W to 90W

B-Grade – PoE

25.5W

C-Grade – PoE 13W

Available In 52-Lead 7mm × 8mm (LTC4270)

and 24-Lead 4mm × 4mm (LTC4271) QFN Packages

LTC4270/LTC4271 FAMILY

LTC4270

GRADE ISOLATION LTPoE

PoE

MAX

DELIVERED

POWER

A Transformer

l l l

90W

B Transformer

l l

25.5W

C Transformer

13W

••

3.3V

3.3V 0.1µF

–54V

100Ω

••

3.3V

1µF

0.1µF

–54V

100Ω

GP0

GP1

MID

RESET

MSD

INT

AUTO

SCL

AD0

AD1

AD2

AD3

AD6

DGND CAP1 CAP2

DND

DPD

CND

CPD

DNA

SENSE1

GATE1

OUT1

LTC4270

DPA

CNA

CPA

XIO0 XIO1

0.22µF

100V

0.22µF

100V

S1B

–54V

42701 TA01a

–54V

S1B

PORTn

PORT1

SDAIN

SDAOUT

LTC4271

NO ISOLATION

REQUIRED ON

C INTERFACE

DD33

2nF 2kV

SENSEn

GATEn

OUTn

AGNDVSSK

0.25Ω

–54V

>47µF

SYSTEM

BULK CAP

L, LT , LT C , LT M , Burst Mode, Linear Technology and the Linear logo are registered trademarks

and LTPoE

is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Summary of content (32 pages)

PAGE 1
LTC4270/LTC4271 12-Port PoE/PoE+/LTPoE++ PSE Controller FEATURES DESCRIPTION 12 Independent PSE Channels n Compliant with IEEE 802.3at Type 1 and 2 n Chipset Provides Electrical Isolation Reduced BOM Cost Eliminates up to 6 High Speed Opto-Couplers Eliminates Isolated 3.3V Power Supply n Low Power Dissipation 0.
PAGE 2
LTC4270/LTC4271 ABSOLUTE MAXIMUM RATINGS LTC4270 (Note 1, Note 4) Supply Voltages AGND – VEE............................................ –0.3V to 80V VSSK (Note 7)...................... VEE – 0.3V to VEE + 0.3V Digital Pins XIOn .................................. VEE – 0.3V to CAP2 + 0.3V Analog Pins SENSEn, GATEn, OUTn ......... VEE – 0.3V to VEE + 80V CAP2 (Note 13) ........................ VEE –0.3V to VEE + 5V CPA, CNA, DPA, DNA...............VEE – 0.3V to VEE + 0.
PAGE 3
LTC4270/LTC4271 PIN CONFIGURATION LTC4271 VEE 52 51 50 49 48 47 46 45 44 43 42 41 38 OUT12 SENSE2 4 CAP1 39 GATE12 OUT1 3 GP0 GATE1 2 VDD33 TOP VIEW 40 SENSE12 MSD SENSE1 1 AUTO NC NC NC NC NC DNA DPA CNA CPA VEE VEE TOP VIEW GP1 LTC4270 24 23 22 21 20 19 37 SENSE11 36 GATE11 AD0 1 OUT2 6 35 OUT11 AD1 2 CAP2 7 34 AGND AD2 3 33 SENSE10 AD3 4 32 GATE10 AD6 5 14 RESET 31 OUT10 MID 6 13 DNC 29 GATE9 OUT4 13 28 OUT9 7 NC GATE4 12 8 15 INT 9 10 11 12 VDD33 30
PAGE 4
LTC4270/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 & 4) SYMBOL PARAMETER MIN TYP MAX UNITS AGND – VEE For IEEE Type 1 Compliant Output For IEEE Type 2 Compliant Output For LTPoE++ Compliant Output l l l 45 51 54.75 Undervoltage Lock-Out AGND – VEE l 20 VDD Supply Voltage VDD – DGND l 3.
PAGE 5
LTC4270/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 & 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Voltage Sense VPG VCUT VLIM Power Good Threshold Voltage VOUTn – VEE l 2 2.4 2.
PAGE 6
LTC4270/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 & 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS XIO VOLX XIO Digital Output Low VXIOn – VEE, IXIOn = 5mA l VOHX XIO Digital Output High VXIOn – VEE, IXIOn = 100µA l 0.
PAGE 7
LTC4270/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.
PAGE 8
LTC4270/LTC4271 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af Power On Sequence in AUTO Pin Mode 0 802.3at Power On Sequence in AUTO Pin Mode 0 AGND FORCED VOLTAGE DETECTION –30 –50 802.3af CLASSIFICATION VEE = –55V CLASS 3 PD POWER ON VEE FORCED VOLTAGE DETECTION –30 –50 –60 FORCED CURRENT DETECTION –20 –40 VEE = –55V CLASS 4 PD 802.
PAGE 9
LTC4270/LTC4271 TYPICAL PERFORMANCE CHARACTERISTICS 802.3at ILIM Threshold vs Temperature 220 802.3at ICUT Threshold vs Temperature 208 VCUT (mV) 832 204 –40 –20 0 162 648 160 640 158 632 156 624 154 616 152 –40 –20 816 100 120 20 40 60 80 TEMPERATURE (°C) 656 0 20 40 60 80 TEMPERATURE (°C) 608 100 120 42701 G10 42701 G09 DC Disconnect Threshold vs Temperature PORT 1 REG 47h = E2h RSENSE = 0.25Ω 2.25 900 8 1.75 7 1.50 700 6 1.
PAGE 10
LTC4270/LTC4271 TEST TIMING DIAGRAMS CLASSIFICATION tDET FORCED-CURRENT VPORTn FORCEDVOLTAGE tME 0V tMEL VOC VMARK 15.5V VCLASS 20.5V tCLE tCLE PD CONNECTED tCLEON tPON VEE INT 42701 F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes VLIM VCUT VSENSEn TO VEE 0V tSTART, tCUT INT 42701 F02 Figure 2. Current Limit Timing VSENSEn TO VEE VMIN INT tMPS tDIS 42701 F03 Figure 3.
PAGE 11
LTC4270/LTC4271 TEST TIMING DIAGRAMS VGATEn VEE tMSD MSD 42701 F04 Figure 4. Shut Down Delay Timing t3 tr t4 tf SCL t2 t5 t6 t7 t8 SDA t1 42701 F05 Figure 5.
PAGE 12
LTC4270/LTC4271 I2C TIMING DIAGRAMS SCL SDA AD6 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 START BY MASTER A6 A5 A4 A3 A2 FRAME 1 SERIAL BUS ADDRESS BYTE A0 ACK D7 A1 ACK BY SLAVE D6 D5 D4 D3 D2 ACK BY SLAVE D1 D0 ACK STOP BY MASTER ACK BY SLAVE FRAME 2 REGISTER ADDRESS BYTE FRAME 3 DATA BYTE 42701 F06 Figure 6.
PAGE 13
LTC4270/LTC4271 PIN FUNCTIONS LTC4270 SENSEn (Pins 1, 4, 8, 11, 15, 18, 21, 24, 30, 33, 37, 40): Port n Current Sense Input. SENSEn monitors the external MOSFET current via a 0.5Ω or 0.25Ω sense resistor between SENSEn and VEE. Whenever the voltage across the sense resistor exceeds the overcurrent detection threshold VCUT, the current limit fault timer counts up.
PAGE 14
LTC4270/LTC4271 PIN FUNCTIONS CPD (Pin 8): Clock Transceiver Positive Input Output (Digital). Connect to CPA through a data transformer. CND (Pin 9): Clock Transceiver Negative Input Output (Digital). Connect to CNA through a data transformer. DPD (Pin 10): Data Transceiver Positive Input Output (Digital). Connect to DPA through a data transformer. DND (Pin 11): Data Transceiver Negative Input Output (Digital). Connect to DNA through a data transformer. VDD33 (Pins 12, 20): VDD IO Power Supply.
PAGE 15
LTC4270/LTC4271 APPLICATIONS INFORMATION OVERVIEW Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W. This initial specification was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.
PAGE 16
LTC4270/LTC4271 APPLICATIONS INFORMATION The LTC4270/LTC4271 chipset implements a proprietary isolation scheme for inter-chip communication. This architecture dramatically reduces BOM cost by replacing expensive opto-isolators and isolated power supplies with a single low-cost transformer. The LTC4270/LTC4271 comes in three grades which support different PD power levels. The A-grade LTC4270/LTC4271 chipset extends PoE power delivery capabilities to LTPoE++ levels.
PAGE 17
LTC4270/LTC4271 APPLICATIONS INFORMATION Extended Power LTPoE++ OPERATING MODES A-grade LTC4270/LTC4271 parts add the capability to autonomously deliver up to 90W of power to the PD. LTPoE++ PDs may forgoe 802.3 LLDP support and rely solely on the LTPoE++ Physical Classification to negotiate power with LTPoE++ PSEs; this greatly simplifies highpower PD implementations.
PAGE 18
LTC4270/LTC4271 APPLICATIONS INFORMATION Reset and the AUTO/MID Pins The initial LTC4270/LTC4271 configuration depends on the state of the AUTO and MID pins during reset. Reset occurs at power-up, or whenever the RESET pin is pulled low or the global Reset All bit is set. Changing the state of AUTO or MID after power-up will not properly change the port behavior of the LTC4270/LTC4271 until a reset occurs.
PAGE 19
LTC4270/LTC4271 APPLICATIONS INFORMATION CURRENT (µA) 275 25kΩ SLOPE 165 VALID PD 0V-2V OFFSET FIRST DETECTION POINT SECOND DETECTION POINT VOLTAGE 42701 F12 Figure 12. PD Detection Table 4. Detection Status MEASURED PD SIGNATURE DETECTION RESULT Incomplete or Not Yet Tested Detect Status Unknown < 2.4k Short Circuit Capacitance > 2.7µF CPD too High 2.
PAGE 20
LTC4270/LTC4271 APPLICATIONS INFORMATION the classification signature current (in this case, Class 3) in the VCLASS range. Table 5 shows the possible classification values. Table 5. 802.3af and 802.3at Classification Values CLASS RESULT Class 0 No Class Signature Present; Treat Like Class 3 Class 1 3W Class 2 7W Class 3 13W Class 4 25.
PAGE 21
LTC4270/LTC4271 APPLICATIONS INFORMATION To aid in diagnosis, the Port Status register will always report the results of the last class pulse, so an invalid Class 4–Class 2 combination would report a second class pulse was run in the High Power Status register (which implies that the first cycle found class 4), and Class 2 in the Port Status register. POWER CONTROL The primary function of the LTC4270/LTC4271 is to control the delivery of power to the PSE port.
PAGE 22
LTC4270/LTC4271 APPLICATIONS INFORMATION Table 6. Example Current Limit Settings INTERNAL REGISTER SETTING (hex) ILIM (mA) RSENSE = 0.5Ω 53 88 106 08 159 89 213 80 266 8A 319 09 372 8B 425 00 478 8E 531 92 584 CB RSENSE = 0.
PAGE 23
LTC4270/LTC4271 APPLICATIONS INFORMATION Port Current Policing Masked Shutdown The LTC4270/LTC4271 can augment tCUT current monitoring with a policing function to track the one second current averages. A port violating the user-specified Port Police Threshold will be shut off with both a tCUT and Police event recorded.
PAGE 24
LTC4270/LTC4271 APPLICATIONS INFORMATION SERIAL DIGITAL INTERFACE I2C ADDRESS Bus Addressing The LTC4270/LTC4271’s primary 7-bit serial bus address is A610A3A2A1A0b, with bit 6 controlled by AD6 and the lower four bits set by the AD3-AD0 pins; this allows up to 10 LTC4270/LTC4271s, on a single bus. Ten LTC4270/ LTC4271 are equivalent to 30 quad PSEs or 120 ports.
PAGE 25
LTC4270/LTC4271 APPLICATIONS INFORMATION For simple devices such as small PoE switches, the isolation requirement can be met by using an isolated main power supply for the entire device. This strategy can be used if the device has no electrically conducting ports other than twisted-pair Ethernet. In this case, the SDAIN and SDAOUT pins can be tied together and will act as a standard I2C/SMBus SDA pin.
PAGE 26
LTC4270/LTC4271 APPLICATIONS INFORMATION 3.3V NO ISOLATION REQUIRED ON I2C INTERFACE 0.1µF XIO0 VDD33 GP0 GP1 100Ω 3.3V • • 100Ω SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 CPA CPD MID RESET MSD AUTO INT • • 100Ω SENSEn LTC4270 100Ω 0.22µF 100V 100Ω S1B GATE1 CAP2 VEE 2nF, 2kV S1B PORT1 DNA T2 –54V OUT1 –54V CAP1 1µF S1B 0.25Ω DPA 3.3V DGND PORTn GATEn CNA T1 100Ω S1B OUTn –54V DPD DND 0.22µF 100V 100Ω 100Ω CND LTC4271 XIO1 0.25Ω AGND SENSE1 VSSK 0.
PAGE 27
LTC4270/LTC4271 APPLICATIONS INFORMATION ESD/Cable Discharge Protection LAYOUT GUIDELINES Ethernet ports can be subject to significant ESD events when long data cables, each potentially charged to thousands of volts, are plugged into the low impedance of the RJ45 jack. To protect against damage, each port requires a pair of clamp diodes; one to AGND and one to VEE (Figure 16). An additional surge suppressor is required for each LTC4270 chip from VEE to AGND.
PAGE 28
DGND CAP1 VDD33 GP0 GP1 MID RESET MSD AUTO INT LTC4271 SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 1µF DND CND DPD CPD 0.1µF 100Ω 3.3V 100Ω 100Ω 3.3V 100Ω 1µF T3 T2 • • 2nF 2000V SMAJ58A • • 1µF –54V –54V –54V + ISOLATED GND –54V ISOLATED 0.1µF >47µF SYSTEM BULK CAP 1µF 100V X7R OUT1 GATE1 SENSE1 OUT12 GATE12 SENSE12 XIO1 VEE VSSK LTC4270 DNA AGND CAP2 CNA DPA XIO0 CPA (NETWORK PHYSICAL LAYER CHIP) PHY RS 0.22µF 100V X7R • • • • T1 S1B • • • • 0.
PAGE 29
LTC4270/LTC4271 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 0.05 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (4 SIDES) R = 0.115 TYP 0.75 0.05 PIN 1 TOP MARK (NOTE 6) PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 0.40 0.10 1 2 2.
PAGE 30
LTC4270/LTC4271 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UKG Package 52-Lead Plastic QFN (7mm × 8mm) (Reference LTC DWG # 05-08-1729 Rev Ø) 7.50 0.05 6.10 0.05 5.50 REF (2 SIDES) 0.70 0.05 6.45 0.05 6.50 REF (2 SIDES) 7.10 0.05 8.50 0.05 5.41 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 0.10 (2 SIDES) 0.75 0.05 0.00 – 0.05 R = 0.
PAGE 31
LTC4270/LTC4271 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 9/11 Updated Absolute Maximum Ratings. Updated Electrical Characteristics. 13 Updated Inrush Control section. 21 Updated Typical Applications. 3/12 Removed temperature readback feature. Changed LTPoE++ power levels from 35W, 45W to 38.7W, 52.7W respectively. Removed Lead Temperature. Updated Electrical Characteristics (removed temperature dots). Clarified AUTO Pin mode relationship to Reset Pin. Modified Related Parts.
PAGE 32
LTC4270/LTC4271 TYPICAL APPLICATION 3.3V 0.1µF 1µF 12 11 VDD33 GP0 GP1 MID RESET MSD AUTO INT LTC4271 SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 XIO0 CPA CPD 100Ω 3.3V • 100Ω 3.3V 100Ω DND • CNA DPA • S1B OUT1 GATE1 SENSE1 RS RJ45 CONNECTOR 0.25Ω, 1% FDMC3612 T3 DNA AGND CAP2 1µF 100V X7R SMAJ58A S1B VEE VSSK 0.1µF • T1 • >47µF SYSTEM BULK CAP + PHY • (NETWORK PHYSICAL LAYER CHIP) • –54V • 0.01µF 200V 75Ω • • • ISOLATED GND • –54V ISOLATED • 2nF 2000V 2 0.