Datasheet

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LTC4274A/LTC4274C

4274acfc

LTPoE

PSE Switches/Routers

LTPoE

PSE Midspans

IEEE 802.3at Type 1 PSE Switches/Routers

IEEE 802.3at Type 1 PSE Midspans

APPLICATIONS

FEATURES DESCRIPTION

Single PoE/PoE

/LTPoE

PSE Controller

The LTC

4274A is a single Power Sourcing Equipment

(PSE) controller capable of delivering up to 90W of LTPoE

power to a compatible LTPoE

Powered Device (PD). A

proprietary detection/classification scheme allows mutual

identification between a LTPoE

PSE and LTPoE

while remaining compatible and interoperable with existing

Type 1 (13W) and Type 2 (25.5W) PDs. The LTC4274A

feature set is a superset of the popular LTC4274. These

PSE controllers feature low-R

external MOSFETs and

0.25 sense resistors which are especially important at

the LTPoE

current levels to maintain the lowest possible

heat dissipation.

The LTC4274C targets fully automatic PSE systems power-

ing Type 1 (up to 13W) PDs.

Advanced power management features include: a 14-bit

current monitoring ADC, DAC-programmable current limit,

and versatile quick port shutdown. PD Discovery uses

a proprietary dual-mode 4-point detection mechanism

ensuring excellent immunity from false PD detection.

The LTC4274A/LTC4274C includes an I

C serial interface

operable up to 1MHz.

The LTC4274A/LTC4274C is available in multiple power

grades, allowing delivered PD power of 13W, 25.5W, 38.7W,

52.7W, 70W and 90W. These controllers are available in a

38-lead 5mm × 7mm QFN package.

Compliant with IEEE 802.3at Type 1 and 2

Low Power Dissipation

0.25Ω Sense Resistance Per Channel

Very High Reliability 4-Point PD Detection

2-Point Forced Voltage

2-Point Forced Current

High Capacitance Legacy Device Detection

1MHz I

C Compatible Serial Control Interface

Midspan Backoff Timer

Supports 2-Pair and 4-Pair Output Power

Available in Multiple Power Grades

LTC4274A-1: LTPoE

™ 38.7W

LTC4274A-2: LTPoE

52.7W

LTC4274A-3: LTPoE

70W

LTC4274A-4: LTPoE

90W

LTC4274C: PoE 13W

Available in 38-Lead 5mm × 7mm QFN Package

TYPICAL APPLICATION

Complete Single-Port Ethernet High Power Source

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

LTPoE

are trademarks of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

4274AC TA01

SCL

SDAIN

SDAOUT

AD0

AD1

AD2

AD3

AGND V

SENSE

–54V

1µF

100V

SMAJ58A

GATE OUT

PORT

0.22µF

100V

S1B

–54V

DGND

INT SHDN

AUTO

MSD

RESET

MID

0.1µF

3.3V

LTC4274A/LTC4274C

Summary of content (30 pages)

PAGE 1
LTC4274A/LTC4274C Single PoE/PoE+/LTPoE++ PSE Controller DESCRIPTION FEATURES n n n n n n n n n The LTC®4274A is a single Power Sourcing Equipment (PSE) controller capable of delivering up to 90W of LTPoE++ power to a compatible LTPoE++ Powered Device (PD). A proprietary detection/classification scheme allows mutual identification between a LTPoE++ PSE and LTPoE++ PD while remaining compatible and interoperable with existing Type 1 (13W) and Type 2 (25.5W) PDs.
PAGE 2
LTC4274A/LTC4274C PIN CONFIGURATION Supply Voltages (Note 1) AGND – VEE ........................................... –0.3V to 80V DGND – VEE ........................................... –0.3V to 80V VDD – DGND ......................................... –0.3V to 5.5V Digital Pins SCL, SDAIN, SDAOUT, INT, SHDN, MSD, AD, RESET, AUTO, MID........... DGND –0.3V to VDD + 0.3V Analog Pins GATE, SENSE, OUT ................ VEE –0.3V to VEE + 80V Operating Temperature Range .................
PAGE 3
LTC4274A/LTC4274C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS VEE Main PoE Supply Voltage AGND – VEE For IEEE Type 1 Compliant Output For IEEE Type 2 Compliant Output For LTPoE++ Compliant Output l l l 45 51 54.
PAGE 4
LTC4274A/LTC4274C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Sense VCUT VLIM VLIM VLIM Overcurrent Sense Voltage VSENSE – VEE, hpen = 01h, cut[5:0] ≥ 4 (Note 12) cutrng = 0 cutrng = 1 l l 9 4.5 9.38 4.69 9.75 4.
PAGE 5
LTC4274A/LTC4274C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 6
LTC4274A/LTC4274C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 7
LTC4274A/LTC4274C TYPICAL PERFORMANCE CHARACTERISTICS Power-On Sequence in AUTO Pin Mode 10 GND PORT VOLTAGE (V) FORCED VOLTAGE DETECTION –30 –40 VDD = 3.3V VEE = –54V LOAD FULLY CHARGED –18.4 VEE PORT CURRENT 200 mA/DIV 802.3af CLASSIFICATION POWER ON –50 –60 VDD = 3.3V VEE = –54V PORT VOLTAGE 20V/DIV –10 –20 GND GND FORCED CURRENT DETECTION 0 802.3af Classification in AUTO Pin Mode Powering Up into a 180μF Load FOLDBACK 0mA GATE VOLTAGE 10V/DIV VEE VEE VDD = 3.
PAGE 8
LTC4274A/LTC4274C TYPICAL PERFORMANCE CHARACTERISTICS 802.3af ILIM Threshold vs Temperature 423 105.75 105.00 –40 0 161 644 160 640 159 636 158 –40 420 120 40 80 TEMPERATURE (°C) 648 80 40 TEMPERATURE (°C) 0 4274AC G10 DC Disconnect Threshold vs Temperature 384 2.0000 381 1.9375 378 93.75 375 93.00 –40 0 7.75 1.8750 7.50 1.8125 7.25 1.7500 –40 372 120 80 40 TEMPERATURE (°C) 8.00 VDD = 3.3V VEE = –54V RSENSE = 0.
PAGE 9
LTC4274A/LTC4274C TYPICAL PERFORMANCE CHARACTERISTICS ADC Noise Histogram Current Readback in Slow Mode ADC INTEGRAL NONLINEARITY (LSBs) 250 200 BIN COUNT 600 1.0 VSENSE – VEE = 110.4mV 150 100 50 0 6139 6141 6143 ADC OUTPUT 6145 500 400 0 200 100 0 500 BIN COUNT 400 300 200 –0.5 100 50 60 0 8532 8533 8534 8535 ADC OUTPUT 8536 0.5 0 –0.5 –1.0 0 10 20 40 30 PORT VOLTAGE (V) 4274AC G21 4274AC G20 INT and SDAOUT Pull-Down Voltage vs Load Current 60 4274AC G22 GND VDD = 3.
PAGE 10
LTC4274A/LTC4274C TEST TIMING DIAGRAMS tDET FORCED-CURRENT CLASSIFICATION FORCEDVOLTAGE tME 0V VPORT tMEL VOC VMARK 15.5V VCLASS 20.5V tCLE tCLE PD CONNECTED tCLEON tPON VEE INT 4274AC F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes VLIM VCUT VSENSE TO VEE 0V tSTART, tICUT INT 4274AC F02 Figure 2. Current Limit Timing VSENSE TO VEE VMIN INT tMPS tDIS 4274AC F03 Figure 3.
PAGE 11
LTC4274A/LTC4274C TEST TIMING DIAGRAMS VGATE tMSD tSHDN VEE MSD or SHDN 4274AC F04 Figure 4. Shut Down Delay Timing t3 tr t4 tf SCL t2 t5 t6 t7 t8 SDA t1 4274AC F05 Figure 5.
PAGE 12
SDA SCL 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A5 A4 A3 A2 A1 A4 A0 ACK ACK BY SLAVE A3 A2 0 0 D5 D3 FRAME 3 DATA BYTE D4 FRAME 1 SERIAL BUS ADDRESS BYTE REPEATED START BY MASTER 1 D6 D2 D6 D5 D3 D1 D0 ACK NO ACK BY MASTER D2 4274AC F06 STOP BY MASTER FRAME 2 DATA BYTE D4 D0 ACK ACK BY SLAVE D1 ACK BY SLAVE AD3 AD2 AD1 AD0 R/W ACK D7 A0 ACK D7 ACK BY SLAVE A1 Figure 7.
PAGE 13
LTC4274A/LTC4274C I2C TIMING DIAGRAMS SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 START BY MASTER D6 D5 D4 D3 ACK BY SLAVE D2 D1 D0 ACK STOP BY MASTER NO ACK BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE 4274AC F08 Figure 8.
PAGE 14
LTC4274A/LTC4274C PIN FUNCTIONS RESET: Chip Reset, Active Low. When the RESET pin is low, the LTC4274A/LTC4274C is held inactive with the port off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4274A/LTC4274C begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1μs wide from resetting the LTC4274A/ LTC4274C.
PAGE 15
LTC4274A/LTC4274C PIN FUNCTIONS GATE: Gate Drive. GATE should be connected to the gate of the external MOSFET for the port. When the MOSFET is turned on, the gate voltage is driven to 12V (typ) above VEE. During a current limit condition, the voltage at GATE will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE is pulled down, turning the MOSFET off and recording a t CUT or tSTART event. OUT: Output Voltage Monitor.
PAGE 16
LTC4274A/LTC4274C OPERATION LTC4274 Product Family The LTC4274 is a third-generation single PSE controller that implements four PSE ports in either an end-point or midspan design. Virtually all necessary circuitry is included to implement an IEEE 802.3at compliant PSE design, requiring only an external power MOSFET and sense resistor; these minimize power loss compared to alternative designs with an on-board MOSFET. The LTC4274 comes in three grades which support different PD power levels.
PAGE 17
LTC4274A/LTC4274C OPERATION When a PD is detected, the PSE optionally looks for a classification signature that tells the PSE the maximum power the PD will draw. The PSE can use this information to allocate power among several ports, police the current consumption of the PD, or to reject a PD that will draw more power that the PSE has available. For a 802.3af PSE, the classification step is optional; if a PSE chooses not to classify a PD, it must assume that the PD is a 13W (full 802.3af power) device.
PAGE 18
LTC4274A/LTC4274C APPLICATIONS INFORMATION Operating Modes Reset and the AUTO/MID Pins The LTC4274A/LTC4274C can operate in one of four modes: manual, semi-auto, AUTO pin, or shutdown. The initial LTC4274A/LTC4274C configuration depends on the state of the AUTO and MID pins during reset. Reset occurs at power-up, or whenever the RESET pin is pulled low or the global Reset All bit is set.
PAGE 19
LTC4274A/LTC4274C APPLICATIONS INFORMATION between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in Figure 11). The PSE may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges. In particular, the PSE must reject standard computer network ports, many of which have 150Ω common-mode termination resistors that will be damaged if power is applied to them (the black region at the left of Figure 11).
PAGE 20
LTC4274A/LTC4274C APPLICATIONS INFORMATION Behavior in AUTO pin mode is similar to semi-auto; however, after Detect Good is reported and the port is classified (if classification is enabled), it is automatically powered on without further intervention. In standalone (AUTO pin) mode, the ICUT and ILIM thresholds are automatically set; see the Reset and the AUTO/MID Pin section for more information.
PAGE 21
LTC4274A/LTC4274C APPLICATIONS INFORMATION 802.3at 2-Event Classification The 802.3at specification defines two methods of classifying a Type 2 PD. The LTC4274A supports 802.3at 2-event classification. The LTC4274C does not support 2-event classification. One method adds extra fields to the Ethernet LLDP data protocol; although the LTC4274A/LTC4274C is compatible with this classification method, it cannot perform classification directly since it doesn’t have access to the data path.
PAGE 22
LTC4274A/LTC4274C APPLICATIONS INFORMATION Current Limit The LTC4274A/LTC4274C port includes two current limiting thresholds (ICUT and ILIM), each with a corresponding timer (tCUT and tLIM). Setting the ICUT and ILIM thresholds depends on several factors: the class of the PD, the voltage of the main supply (VEE), the type of PSE (Type 1 or Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and whether or not the system is required to implement class enforcement.
PAGE 23
LTC4274A/LTC4274C APPLICATIONS INFORMATION The LTC4274A/LTC4274C will support current levels well beyond the maximum values in the 802.3at specification. The shaded areas in Table 6 indicate settings that may require a larger external MOSFET, additional heat sinking, or enabling tLIM . MOSFET Fault Detection The LTC4274A/LTC4274C PSE port is designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged.
PAGE 24
LTC4274A/LTC4274C APPLICATIONS INFORMATION SERIAL DIGITAL INTERFACE EXTERNAL COMPONENT SELECTION Overview Power Supplies and Bypassing The LTC4274A/LTC4274C communicates with the host using a standard SMBus/I2C 2-wire interface. The LTC4274A/ LTC4274C is a slave-only device, and communicates with the host master using the standard SMBus protocols. Interrupts are signaled to the host via the INT pin.
PAGE 25
LTC4274A/LTC4274C APPLICATIONS INFORMATION L3 100μH SUMIDA CDRH5D28-101NC L4 10μH SUMIDA CDRH4D28-100NC D28 B1100 3.3V AT 400mA C76 10μF 63V + R51 4.7k 1% C78 0.22μF 100V 5 VCC C77 0.22μF 100V 1 R58 10Ω R60 10Ω C74 100μF 6.3V C75 10μF 16V R53 4.7k 1% R54 56k C79 2200pF ITH/RUN C73 10μF 6.3V R52 3.32k 1% Q13 FMMT723 NGATE 6 Q14 FMMT723 Q15 FDC2512 LTC3803 3 VFB SENSE 4 GND 2 R57 1k R55 806Ω 1% R59 0.100Ω 1%, 1W R56 47.5k 1% VEE 4274AC F15 Figure 15.
PAGE 26
LTC4274A/LTC4274C APPLICATIONS INFORMATION 0.1μF 2k U2 2001 VDD CPU U1 ISOLATED 3.3V SCL 0.1μF 2001 2k SDA HCPL-063L TO CONTROLLER + 10μF U3 2001 ISOLATED GND VDD LTC4274A/ INT LTC4274C SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 2001 SMBALERT 0.1μF GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L 4274AC F16 HCPL-063L Figure 16.
PAGE 27
LTC4274A/LTC4274C APPLICATIONS INFORMATION External MOSFET ESD/Cable Discharge Protection Careful selection of the power MOSFET is critical to system reliability. LTC recommends either Fairchild IRFM120A, FDT3612, FDMC3612 or Philips PHT6NQ10T for their proven reliability in Type 1 and Type 2 PSE applications. Non-standard applications that provide more current than the 850mA IEEE maximum may require heat sinking and other MOSFET design considerations.
PAGE 28
LTC4274A/LTC4274C PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 p 0.05 5.50 p 0.05 5.15 ± 0.05 4.10 p 0.05 3.00 REF 3.15 ± 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 5.5 REF 6.10 p 0.05 7.50 p 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 0.75 p 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.
PAGE 29
LTC4274A/LTC4274C REVISION HISTORY REV DATE DESCRIPTION A 9/11 Changed GATE typ voltage to 12V. B C 1/12 8/12 PAGE NUMBER 3, 15, 21 Revised VILD text under Digital Interface. 4 Table 4 reference and caption changed to Table 5. 20 Revised power supply voltage figures under Power Supplies and Bypassing. 24 Text CUT/LIM changed to ICUT/ILIM in the Related Parts section. 30 Specified SMAJ58A for Zener diode. 30 Changed LTPoE++ power levels from 35W, 45W to 38.7W, 52.7W respectively.
PAGE 30
LTC4274A/LTC4274C TYPICAL APPLICATION One Complete Isolated Powered Ethernet Port ISOLATED 3.3V ISOLATED GND 0.1μF DGND AGND 2k U2 200Ω LTC4274A/ LTC4274C SCL SDAIN SDAOUT INT VDD CPU U1 SCL VEE 2k 200Ω 1μF 100V X7R TO CONTROLLER 0.22μF 100V X7R VDD FB1 SENSE GATE OUT FB2 S1B RSENSE 0.25Ω SDA Q1 HCPL-063L U3 SMAJ58A 200Ω ISOLATED –54V S1B RJ45 CONNECTOR T1 s 200Ω SMBALERT s s s s 0.01μF 200V 75Ω 0.01μF 200V 75Ω 75Ω 75Ω 1 2 3 4 5 6 7 8 s PHY 0.