Datasheet

LTC4274A/LTC4274C
12
4274acfc
I
2
C TIMING DIAGRAMS
Figure 6. Writing to a Register
Figure 7. Reading from a Register
SCL
SDA
4274AC F06
001
AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0
R/W
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
STOP BY
MASTER
SCL
SDA
001
AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0
R/W
ACK
ACK
001
AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0
R/W
ACK
ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
4274AC F07
STOP BY
MASTER
REPEATED
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE