Datasheet

LTC4274A/LTC4274C
14
4274acfc
PIN FUNCTIONS
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4274A/LTC4274C is held inactive with the port
off and all internal registers reset to their power-up states.
When RESET is pulled high, the LTC4274A/LTC4274C
begins normal operation. RESET can be connected to
an external capacitor or RC network to provide a power
turn-on delay. Internal filtering of the RESET pin prevents
glitches less than 1µs wide from resetting the LTC4274A/
LTC4274C. Internally pulled up to V
DD
.
MID: Midspan Mode Input. When high, the LTC4274A/
LTC4274C acts as a midspan device. Internally pulled
down to DGND.
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4274A/LTC4274C.
It will return to a high impedance state when bits 6 or 7
are set in the Reset PB register (1Ah). The INT signal can
be used to generate an interrupt to the host processor,
eliminating the need for continuous software polling.
Individual INT events can be disabled using the Int Mask
register (01h). See the LTC4274A/LTC4274C Software
Programming documentation for more information. The
INT pin is only updated between I
2
C transactions.
SCL: Serial Clock Input. High impedance clock input for the
I
2
C serial interface bus. SCL must be tied high if not used.
SDAOUT: Serial Data Output, Open Drain Data Output for
the I
2
C Serial Interface Bus. The LTC4274A/LTC4274C
uses two pins to implement the bidirectional SDA function
to simplify optoisolation of the I
2
C bus. To implement a
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAOUT should be grounded or left floating if
not used. See the Applications Information section for
more information.
SDAIN: Serial Data Input. High impedance data input for
the I
2
C serial interface bus. The LTC4274A/LTC4274C
uses two pins to implement the bidirectional SDA function
to simplify optoisolation of the I
2
C bus. To implement a
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAIN must be tied high if not used. See the
Applications Information section for more information.
AD3: Address Bit 3. Tie the address pins high or low to set
the I
2
C serial address to which the LTC4274A/LTC4274C
responds. This address will be 010A
3
A
2
A
1
A
0
b. Internally
pulled up to V
DD
.
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
DGND: Digital Ground. DGND is the return for the V
DD
supply.
V
DD
: Logic Power Supply. Connect to a 3.3V power supply
relative to DGND. V
DD
must be bypassed to DGND near
the LTC4274A/LTC4274C with at least a 0.1µF capacitor.
SHDN: Shutdown, Active Low. When pulled low, SHDN
shuts down the port, regardless of the state of the internal
registers. Pulling SHDN low is equivalent to setting the
Reset Port bit in the Reset Pushbutton register (1Ah).
Internal filtering of the SHDN pin prevents glitches less
than 1µs wide from resetting the port. Internally pulled
up to V
DD
.
AGND: Analog Ground. AGND is the return for the V
EE
supply.
SENSE: Current Sense Input. SENSE monitors the exter-
nal MOSFET current via a 0.5Ω or 0.25 sense resistor
between SENSE and V
EE
. Whenever the voltage across
the sense resistor exceeds the overcurrent detection
threshold V
CUT
, the current limit fault timer counts up. If
the voltage across the sense resistor reaches the current
limit threshold V
LIM
, the GATE pin voltage is lowered to
maintain constant current in the external MOSFET. See
the Applications Information section for further details.