Datasheet

LTC4274A/LTC4274C
15
4274acfc
Overview
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE spec, known as 802.3af, allowed for 48V DC
power at up to 13W. This initial spec was widely popular,
but 13W was not adequate for some requirements. In
2009, the IEEE released a new standard, known as 802.3at
or PoE
+
, increasing the voltage and current requirements
to provide 25W of power.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE, or
power sourcing equipment, while a device that draws power
from the network is known as a PD, or powered device.
PSEs come in two types: Endpoints (typically network
switches or routers), which provide data and power; and
Midspans, which provide power but pass through data.
Midspans are typically used to add PoE capability to existing
non-PoE networks. PDs are typically IP phones, wireless
access points, security cameras, and similar devices.
PoE
++
Evolution
Even during the process of creating the IEEE PoE
+
25.5W
specification, it became clear that there was a significant
and increasing need for more than 25.5W of delivered
power. The LTC4274A family responds to this market by
allowing a reliable means of providing up to 90W of deliv-
ered power to a LTPoE
++
PD. The LTPoE
++
specification
provides reliable detection and classification extensions to
the existing IEEE PoE technique that are backward com-
patible and interoperable with existing Type 1 and Type 2
PDs. Unlike other proprietary PoE
++
solutions, Linear’s
LTPoE
++
solution provides mutual identification between
the PSE and PD. This ensures that the LTPoE
++
PD knows
it may use the requested power at start-up because it has
detected a LTPoE
++
PSE. LTPoE
++
PSEs can differentiate
between a LTPoE
++
PD and all other types of IEEE compli-
ant PDs allowing LTPoE
++
PSEs to remain compliant and
interoperable with existing equipment.
PIN FUNCTIONS
GATE: Gate Drive. GATE should be connected to the gate
of the external MOSFET for the port. When the MOSFET
is turned on, the gate voltage is driven to 12V (typ) above
V
EE
. During a current limit condition, the voltage at GATE
will be reduced to maintain constant current through the
external MOSFET. If the fault timer expires, GATE is pulled
down, turning the MOSFET off and recording a t
CUT
or
t
START
event.
OUT: Output Voltage Monitor. OUT should be connected
to the output port. A current limit foldback circuit limits
the power dissipation in the external MOSFET by reduc-
ing the current limit threshold when the drain-to-source
voltage exceeds 10V. The Power Good bit is set when the
voltage from OUT to V
EE
drops below 2.4V (typ). A 500k
resistor is connected internally from OUT to AGND when
the port is idle.
V
EE
: Main Supply Input. Connect to a –45V to –57V
supply, relative to AGND.
AUTO: AUTO Pin Mode Input. AUTO pin mode allows the
LTC4274A/LTC4274C to detect and power up a PD even
if there is no host controller present on the I
2
C bus. The
voltage of the AUTO pin determines the state of the internal
registers when the LTC4274A/LTC4274C is reset or comes
out of V
DD
UVLO (see the LTC4274A/LTC4274C Software
Programming documentation). The states of these register
bits can subsequently be changed via the I
2
C interface.
The real-time state of the AUTO pin is read at bit 0 in the
Pin Status register (11h). Internally pulled down to DGND.
Must be tied locally to either V
DD
or DGND.
MSD: Maskable Shutdown Input. Active low. When pulled
low, all ports that have their corresponding mask bit set
in the Misc Config register (17h) will be reset, equivalent
to pulling the SHDN pin low. Internal filtering of the MSD
pin prevents glitches less than 1µs wide from resetting
ports. Internally pulled up to V
DD
.
OPERATION