Datasheet

LTC4274A/LTC4274C
24
4274acfc
SERIAL DIGITAL INTERFACE
Overview
The LTC4274A/LTC4274C communicates with the host us-
ing a standard SMBus/I
2
C 2-wire interface. The LTC4274A/
LTC4274C is a slave-only device, and communicates with
the host master using the standard SMBus protocols.
Interrupts are signaled to the host via the INT pin. The
timing diagrams (Figures 5 through 9) show typical com-
munication waveforms and their timing relationships. More
information about the SMBus data protocols can be found
at www.smbus.org.
The LTC4274A/LTC4274C requires both the V
DD
and V
EE
supply rails to be present for the serial interface to function.
Bus Addressing
The LTC4274A/LTC4274C’s primary serial bus address is
010xxxxb, with the lower four bits set by the AD3-AD0
pins; this allows up to 16 LTC4274A/LTC4274Cs on a
single bus. All LTC4274A/LTC4274Cs also respond to
the address 0110000b, allowing the host to write the
same command (typically configuration commands) to
multiple LTC4274A/LTC4274Cs in a single transaction. If
the LTC4274A/LTC4274C is asserting the INT pin, it will
also respond to the alert response address (0001100b)
per the SMBus spec.
Interrupts and SMBALERT
Most LTC4274A/LTC4274C port events can be configured
to trigger an interrupt, asserting the INT pin and alerting
the host to the event. This removes the need for the host
to poll the LTC4274A/LTC4274C, minimizing serial bus
traffic and conserving host CPU cycles. Multiple LTC4274A/
LTC4274Cs can share a common INT line, with the host
using the SMBALERT protocol (ARA) to determine which
LTC4274A/LTC4274C caused an interrupt.
Register Description
For information on serial bus usage and device configura-
tion and status, refer to the LTC4274A/LTC4274C Software
Programming documentation.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4274A/LTC4274C requires two supply voltages to
operate. V
DD
requires 3.3V (nominally) relative to DGND.
V
EE
requires a negative voltage of between –45V and –57V
for Type 1 PSEs, –51V to –57V for Type 2 PSEs or –54.75V
to –57V for LTPoE
++
PSEs, relative to AGND. The relation-
ship between the two grounds is not fixed; AGND can be
referenced to any level from V
DD
to DGND, although it
should typically be tied to either V
DD
or DGND.
V
DD
provides power for most of the internal LTC4274A/
LTC4274C circuitry, and draws a maximum of 3mA. A
ceramic decoupling cap of at least 0.1F should be placed
from V
DD
to DGND, as close as practical to each LTC4274A/
LTC4274C chip.
Figure 14 shows a three component low dropout regula-
tor for a negative supply to DGND generated from the
negative V
EE
supply. V
DD
is tied to AGND and DGND is
negative referenced to AGND. This regulator drives a single
LTC4274A/LTC4274C device. In Figure 15, DGND is tied
to AGND in this boost converter circuit for a positive V
DD
supply of 3.3V above AGND. This circuit can drive multiple
LTC4274A/LTC4274C devices and opto couplers.
APPLICATIONS INFORMATION
Figure 14. Negative LDO to DGND
4274AC F14
R5
750k
D1
CMHZ4687-4.3V
C1
0.1µF
Q2
CMPTA92
V
EE
V
DD
LTC4274A/
LTC4274C
AGND
V
EE
AGND
DGND