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LTC4274

4274fd

PSE Switches/Routers

PSE Midspans

APPLICATIONS

FEATURES DESCRIPTION

Single PoE

PSE Controller

The LTC

4274 is a single power sourcing equipment con-

troller designed for use in IEEE 802.3 Type 1 and Type 2

(high power) compliant Power over Ethernet systems.

External power MOSFETs enhance system reliability and

minimize channel resistance, cutting power dissipation and

eliminating the need for heatsinks even at Type 2 power

levels. External power components also allow use at very

high power levels while remaining otherwise compatible

with the IEEE standard. 80V-rated port pins provide robust

protection against external faults.

The LTC4274 includes advanced power management

features, including current and voltage readback and pro-

grammable I

CUT

and I

LIM

thresholds. Available C libraries

simplify software development; an optional AUTO pin mode

provides fully IEEE-compliant standalone operation with

no software required. Proprietary 4-point PD detection

circuitry minimizes false PD detection while supporting

legacy phone operation. Midspan operation is supported

with built-in 2-event classification and backoff timing.

Host communication is via a 1MHz I

C serial interface.

The LTC4274 is available in a 5mm × 7mm QFN package

that significantly reduces board space compared with

competing solutions.

Compliant with IEEE 802.3at Type 1 and 2

0.34Ω Total Channel Resistance

130mW/Port at 600mA

Advanced Power Management

8-Bit Programmable Current Limit (I

LIM

)

7-Bit Programmable Overload Currents (I

CUT

)

Fast Shutdown

14.5-Bit Port Current/Voltage Monitoring

2-Event Classification

Very High Reliability 4-Point PD Detection:

2-Point Forced Voltage

2-Point Forced Current

High Capacitance Legacy Device Detection

LTC4259A-1 and LTC4266 SW Compatible

1MHz I

C Compatible Serial Control Interface

Midspan Backoff Timer

Supports Proprietary Power Levels Above 25W

Available in 38-Pin 5mm × 7mm QFN Package

TYPICAL APPLICATION

Complete Ethernet High Power Source

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT and LTPoE

are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

4274 TA01

SCL

SDAIN

SDAOUT

AD0

AD1

AD2

AD3

AGND V

SENSE

–54V

1µF

100V

SMAJ58A

GATE OUT

PORT

0.22µF

100V

S1B

–54V

DGND

INT SHDN

AUTO

MSD

RESET

MID

0.1µF

3.3V

LTC4274

Summary of content (28 pages)

PAGE 1
LTC4274 Single PoE+ PSE Controller FEATURES DESCRIPTION n The LTC®4274 is a single power sourcing equipment controller designed for use in IEEE 802.3 Type 1 and Type 2 (high power) compliant Power over Ethernet systems. External power MOSFETs enhance system reliability and minimize channel resistance, cutting power dissipation and eliminating the need for heatsinks even at Type 2 power levels.
PAGE 2
LTC4274 ABSOLUTE MAXIMUM RATINGS Supply Voltages (Note 1) AGND – VEE ........................................... –0.3V to 80V DGND – VEE ............................................... –0.3V to 80V VDD – DGND.............................................. –0.3V to 5.5V Digital Pins SCL, SDAIN, SDAOUT, INT, SHDN, MSD, ADn, RESET, AUTO, MID........... DGND –0.3V to VDD + 0.3V Analog Pins GATE, SENSE, OUT ................ VEE –0.3V to VEE + 80V Operating Temperature Range LTC4274C .............................
PAGE 3
LTC4274 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL VDD PARAMETER CONDITIONS Main PoE Supply Voltage AGND – VEE For IEEE Type 1 Complaint Output For IEEE Type 2 Complaint Output MIN l l 45 51 Undervoltage Lock-out Level l 20 VDD Supply Voltage l 3.
PAGE 4
LTC4274 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Sense VCUT VLIM VLIM VLIM VSENSE – VEE, icut1 = hpen = 00h hpen = 01h, cut[5:0] ≥ 4 (Note 12) cutrng = 0 cutrng = 1 l 180 188 196 mV l l 9 4.5 9.38 4.69 9.75 4.
PAGE 5
LTC4274 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 6
LTC4274 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted.
PAGE 7
LTC4274 TYPICAL PERFORMANCE CHARACTERISTICS Power On Sequence in AUTO Pin Mode 802.3af Classification in AUTO Pin Mode Powering Up into a 180μF Load GND 10 GND FORCED CURRENT DETECTION 0 GND PORT VOLTAGE (V) FORCED VOLTAGE DETECTION –20 –30 –40 PORT 1 VDD = 3.3V VEE = –54V –50 –60 VDD = 3.3V VEE = –54V PORT VOLTAGE 20V/DIV –10 LOAD FULLY CHARGED –18.4 VEE PORT CURRENT 200 mA/DIV 802.3af CLASSIFICATION POWER ON FOLDBACK 0mA GATE VOLTAGE 10V/DIV VEE VEE VDD = 3.
PAGE 8
LTC4274 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af ILIM Threshold vs Temperature 163 162 429 426 652 VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 47h = E2h 648 161 644 160 640 159 636 423 105.75 105.00 –40 0 158 –40 420 120 40 80 TEMPERATURE (°C) 0 40 80 TEMPERATURE (°C) DC Disconnect Threshold vs Temperature 802.3af ICUT Threshold vs Temperature 384 2.0000 381 1.9375 378 93.75 375 93.00 –40 0 7.75 1.8750 7.50 1.8125 7.25 1.7500 –40 372 120 80 40 TEMPERATURE (°C) 8.
PAGE 9
LTC4274 TYPICAL PERFORMANCE CHARACTERISTICS ADC Noise Histogram Current Readback in Slow Mode 1.0 ADC INTEGRAL NONLINEARITY (LSBs) VSENSE – VEE = 110.4mV 250 BIN COUNT 200 150 100 50 6145 400 0 200 100 265 ADC Integral Nonlinearity Voltage Readback in Slow Mode ADC INTEGRAL NONLINEARITY (LSBs) 500 BIN COUNT 400 300 200 –0.5 100 50 264 1.0 AGND – VOUT = 48.3V 0.5 0.5 0 –0.5 –1.0 0 60 8532 8533 8534 8535 ADC OUTPUT 4274 G20 8536 10 0 20 40 30 PORT VOLTAGE (V) GND VDD = 3.
PAGE 10
LTC4274 TEST TIMING DIAGRAMS tDET CLASSIFICATION FORCEDVOLTAGE FORCED-CURRENT tME1 0V VPORT tME2 VOC VMARK 15.5V VCLASS 20.5V tCLE1 tCLE2 PD CONNECTED tCLE3 tPON tDETDLY VEE INT 4274 F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes VLIM VCUT VSENSE TO VEE VSENSE TO VEE 0V VMIN tSTART, tICUT INT INT tMPS tDIS 4274 F03 4274 F02 Figure 3. DC Disconnect Timing Figure 2.
PAGE 11
LTC4274 I2C TIMING DIAGRAMS SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 START BY MASTER A6 A5 A4 A3 A2 ACK BY SLAVE FRAME 1 SERIAL BUS ADDRESS BYTE A0 ACK D7 A1 D6 D5 D4 D3 D2 D1 ACK BY SLAVE D0 ACK STOP BY MASTER ACK BY SLAVE FRAME 2 REGISTER ADDRESS BYTE FRAME 3 DATA BYTE 4274 F06 Figure 6.
PAGE 12
LTC4274 PIN FUNCTIONS RESET: Chip Reset, Active Low. When the RESET pin is low, the LTC4274 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4274 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1μs wide from resetting the LTC4274. Internally pulled up to VDD. MID: Midspan Mode Input.
PAGE 13
LTC4274 PIN FUNCTIONS the power dissipation in the external MOSFET by reducing the current limit threshold when the drain-to-source voltage exceeds 10V. The Power Good bit is set when the voltage from OUT to VEE drops below 2.4V (typ). A 500k resistor is connected internally from OUT to AGND when the port is idle. (see the LTC4274 Software Programming documentation). The states of these register bits can subsequently be changed via the I2C interface.
PAGE 14
LTC4274 OPERATION Overview compared to alternative designs with on-board MOSFETs and increase system reliability in the event a single channel is damaged. Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W.
PAGE 15
LTC4274 OPERATION power that the PSE has available. The classification step is optional; if a PSE chooses not to classify a PD, it must assume that the PD is a 13W (full 802.3af power) device. without software or PCB layout changes if only port 1 was used; only minor BOM changes are required to implement a fully compliant 802.3at design. New in 802.3at Because of the backwards compatibility features, some of the internal registers are redundant or unused when the LTC4274 is operated as recommended.
PAGE 16
LTC4274 APPLICATIONS INFORMATION Operating Modes The LTC4274 can operate in one of four modes: manual, semi-auto, AUTO pin, or shutdown. Table 1.
PAGE 17
LTC4274 APPLICATIONS INFORMATION Detection Overview To avoid damaging network devices that were not designed to tolerate DC voltage, a PSE must determine whether the connected device is a real PD before applying power. The IEEE specification requires that a valid PD have a commonmode resistance of 25k ±5% at any port voltage below 10V. The PSE must accept resistances that fall between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in Figure 11).
PAGE 18
LTC4274 APPLICATIONS INFORMATION If the port is in semi-auto mode and high power operation is enabled, the port will not turn on in response to a power-on command unless the current detect result is detect good. Any other detect result will generate a tSTART fault if a power-on command is received. If the port is not in high power mode, it will ignore the detection result and apply power when commanded, maintaining backwards compatibility with the LTC4259A.
PAGE 19
LTC4274 APPLICATIONS INFORMATION the OUT pin and measuring the resulting current; it then reports the discovered class in the Port Status register. If the LTC4274 is in AUTO pin mode, it will additionally use the classification result to set the ICUT and ILIM thresholds. See the Reset and the AUTO/MID Pin section for more information. The classification circuitry is disabled when the port is initially powered up with the AUTO pin low, in shutdown mode, or when the corresponding Class Enable bit is cleared.
PAGE 20
LTC4274 APPLICATIONS INFORMATION current reaches the inrush current limit level (typically 450mA), at which point the GATE pin will be servoed to maintain the specified IINRUSH current. During this inrush period, a timer (tSTART) runs. When output charging is complete, the port current will fall and the GATE pin will be allowed to continue rising to fully enhance the MOSFET and minimize its on-resistance. The final VGS is nominally 12V.
PAGE 21
LTC4274 APPLICATIONS INFORMATION even at extended 802.3at power levels. Current limit and foldback behavior are programmable. Figure 14 shows MOSFET power dissipation with 802.3af-style foldback compared with a typical MOSFET SOA curve; Figure 15 demonstrates how two-stage foldback keeps the FET within its SOA under the same conditions. Table 5 gives examples of recommended ILIM register settings. The LTC4274 will support current levels well beyond the maximum values in the 802.3at specification.
PAGE 22
LTC4274 APPLICATIONS INFORMATION timer resets and will start counting from the beginning if the undercurrent condition returns. As long as the PD exceeds the minimum current level more often than tDIS, it will stay powered. the host via the INT pin. The Timing Diagrams (Figures 5 through 9) show typical communication waveforms and their timing relationships. More information about the SMBus data protocols can be found at www.smbus.org.
PAGE 23
LTC4274 APPLICATIONS INFORMATION VDD provides power for most of the internal LTC4274 circuitry, and draws a maximum of 3mA. A ceramic decoupling cap of at least 0.1μF should be placed from VDD to DGND, as close as practical to each LTC4274 chip. VEE is the main supply that provides power to the PD. Because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply.
PAGE 24
LTC4274 APPLICATIONS INFORMATION 0.1MF 2k U2 2007 VDD CPU U1 ISOLATED 3.3V SCL 0.1MF 2007 2k SDA HCPL-063L TO CONTROLLER + 10MF U3 2007 ISOLATED GND VDD LTC4274 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 2007 SMBALERT 0.1MF GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L 4274 F18 HCPL-063L Figure 18. Opto-Isolating the I2C Bus isolated from each other, provided that the segments are connected to devices residing within a single building on a single power distribution system.
PAGE 25
LTC4274 APPLICATIONS INFORMATION Sense Resistor ESD/Cable Discharge Protection The LTC4274 is designed to use either 0.5Ω or 0.25Ω current sense resistors. For new designs 0.25Ω is recommended to reduce power dissipation; the 0.5Ω option is intended for existing systems where the LTC4274 is used as a drop-in replacement for the LTC4258 or LTC4259A. The lower sense resistor values reduce heat dissipation.
PAGE 26
LTC4274 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 p 0.05 5.50 p 0.05 5.15 ± 0.05 4.10 p 0.05 3.00 REF 3.15 ± 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 5.5 REF 6.10 p 0.05 7.50 p 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 0.75 p 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 3.
PAGE 27
LTC4274 REVISION HISTORY REV DATE DESCRIPTION A 4/11 Revised entire data sheet. PAGE NUMBER B 6/11 Added separate tLIM entry and revised tCUT and tDIS entries in the Electrical Characteristics section. 1 to 28 Revised curves G17, G19 and G21 in the Typical Performance Characteristics section. 9 Revised the AUTO pin description in the Pin Functions section.
PAGE 28
LTC4274 TYPICAL APPLICATION One Complete Isolated Powered Ethernet Port ISOLATED 3.3V ISOLATED GND 0.1μF DGND AGND 2k U2 200Ω LTC4274 FB1 SCL SDAIN SDAOUT INT VDD CPU U1 SCL VEE 2k 200Ω 1μF 100V X7R TO CONTROLLER 0.22μF 100V X7R VDD SENSE GATE OUT FB2 S1B RSENSE 0.25Ω SDA Q1 HCPL-063L U3 SMAJ58A 200Ω ISOLATED –54V S1B RJ45 CONNECTOR T1 s 200Ω SMBALERT s s s s 0.01μF 200V 75Ω 0.01μF 200V 75Ω 75Ω 75Ω 1 2 3 4 5 6 7 8 s PHY 0.