Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsInterface ICsInterface IC - buffer amplifiers, accelerators I²C hot swap 400 kHz MSOP 8

LTC4300-1/LTC4300-2

430012fb

For more information www.linear.com/LTC4300-1

Typical applicaTion

FeaTures DescripTion

Hot Swappable

2-Wire

Bus Buffers

The LT C

4300 series hot swappable 2-wire bus buffers

allow I/O card insertion into a live backplane without cor-

ruption of

the data and clock busses. When the connection

is made, the LTC4300-1/LTC4300-2 provide bidirectional

buffering, keeping the backplane and card capacitances

isolated. Rise time accelerator circuitry* allows the use of

weaker DC pull-up currents while still meeting rise time

requirements. During insertion, the SDA and SCL lines are

precharged to 1V to minimize bus disturbances.

The LTC4300-1 incorporates a CMOS threshold digital

ENABLE input

pin, which forces the part into a low current

mode when driven to ground and sets normal operation

when driven to V

. It also includes an open drain READY

output pin, which indicates that the backplane and card

sides are connected together. The LTC4300-2 replaces

the ENABLE pin with a dedicated supply voltage pin, V

CC2

for the card side, providing level shifting between 3.3V

and 5V systems. Both the backplane and card may be

powered with supply voltages ranging from 2.7V to 5.5V,

with no constraints on which supply voltage is higher.

The LTC4300-2 also replaces the READY pin

with a

digital

CMOS input pin, ACC, which enables and disables the rise

time accelerator currents.

The LTC4300 is available in a small 8-lead MSOP package.

Input–Output Connection t

PLH

applicaTions

Bidirectional Buffer for SDA and SCL Lines

Increases Fanout

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal From Backplane

Isolates Input SDA and SCL Lines From Output

Compatible with I

C, I

C Fast Mode and SMBus

Standards (Up to 400kHz Operation)

Low I

Chip Disable: <1µA (LTC4300-1)

READY Open-Drain Output (LTC4300-1)

1V Precharge on All SDA and SCL Lines

Supports Clock Stretching, Arbitration and

Synchronization

5V to 3.3V Level Translation (LTC4300-2)

High Impedance SDA, SCL Pins for V

= 0V

Small MSOP 8-Lead Package

Hot Board Insertion

Servers

Capacitance Buffer/Bus Extender

Desktop Computer

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks

are

the property of their respective owners. *Protected by U.S. Patents, including 6650174.

24k

3.3V

24k

ENABLE

SCLIN SCLOUT

SDAIN SDAOUT

1 5

6 7

3 2

GND

LTC4300-1

READY

0.01µF

C2* C4*

C5*

C3*

430012 TA01a

24k

*CAPACITORS NOT REQUIRED

IF BUS IS SUFFICIENTLY LOADED

OUTPUT SIDE

50pF

0.5V/DIV

430012 TA01b

INPUT SIDE

150pF

200ns/DIV

Summary of content (18 pages)

PAGE 1
LTC4300-1/LTC4300-2 Hot Swappable 2-Wire Bus Buffers Description Features n n n n n n n n n n n Bidirectional Buffer for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal From Backplane Isolates Input SDA and SCL Lines From Output Compatible with I2C, I2C Fast Mode and SMBus Standards (Up to 400kHz Operation) Low ICC Chip Disable: <1µA (LTC4300-1) READY Open-Drain Output (LTC4300-1) 1V Precharge on All SDA and SCL Lines Supports Clock Stretching
PAGE 2
LTC4300-1/LTC4300-2 Absolute Maximum Ratings Pin Configuration (Note 1) VCC to GND...................................................– 0.5V to 7V VCC2 to GND (LTC4300-2)............................. –0.5V to 7V SDAIN, SCLIN, SDAOUT, SCLOUT................. –0.5V to 7V READY, ENABLE (LTC4300-1)....................... –0.5V to 7V ACC (LTC4300-2).......................................... –0.5V to 7V Operating Temperature Range LTC4300-1C/LTC4300-2C......................... 0°C to 70°C LTC4300-1I/LTC4300-2I.
PAGE 3
LTC4300-1/LTC4300-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VDIS Disable Threshold Voltage LTC4300-1, ENABLE Pin IEN ENABLE Input Current ENABLE from 0V to VCC, LTC4300-1 ±0.
PAGE 4
LTC4300-1/LTC4300-2 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 3: The connection circuitry always regulates its output to a higher voltage than its input.
PAGE 5
LTC4300-1/LTC4300-2 Pin Functions ENABLE/VCC2 (Pin 1): Chip Enable Pin/Card Supply Voltage. For the LTC4300-1, this is a digital CMOS threshold input pin. Grounding this pin puts the part in a low current (<1µA) mode. It also disables the rise time accelerators, disables the bus precharge circuitry, drives READY low, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. Drive ENABLE all the way to VCC for normal operation. Connect ENABLE to VCC if this feature is not being used.
PAGE 6
LTC4300-1/LTC4300-2 Block Diagram LTC4300-1 2-Wire Bus Buffer and Hot Swap™ Controller 2mA 2mA SLEW RATE DECTECTOR SLEW RATE DECTECTOR 8 VCC BACKPLANE-TO-CARD CONNECTION SDAIN 6 CONNECT 74 SDAOUT CONNECT CONNECT ENABLE 100k RCH1 100k RCH3 1V PRECHARGE 100k RCH2 100k RCH4 2mA 2mA SLEW RATE DECTECTOR SLEW RATE DECTECTOR BACKPLANE-TO-CARD CONNECTION SCLIN 3 CONNECT 2 SCLOUT + CONNECT – + + – – 0.55VCC/ 0.45VCC STOP BIT AND BUS IDLE 0.5µA + 0.55VCC/ 0.
PAGE 7
LTC4300-1/LTC4300-2 Block Diagram LTC4300-2 2-Wire Bus Buffer and Hot Swap Controller VCC 8 2mA ACC 2mA SLEW RATE DECTECTOR 1 VCC2 SLEW RATE DECTECTOR BACKPLANE-TO-CARD CONNECTION SDAIN 6 CONNECT 74 SDAOUT CONNECT CONNECT 100k RCH1 100k RCH3 1V PRECHARGE 100k RCH2 100k RCH4 2mA ACC 2mA SLEW RATE DECTECTOR SLEW RATE DETECTOR 5 ACC BACKPLANE-TO-CARD CONNECTION SCLIN 3 CONNECT 2 SCLOUT + CONNECT – 0.55VCC2/ 0.45VCC2 + + – – STOP BIT AND BUS IDLE 0.5µA + 0.55VCC/ 0.
PAGE 8
LTC4300-1/LTC4300-2 Operation Start-Up When the LTC4300 first receives power on its VCC pin, either during power-up or during hot swapping, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above 2.5V. For the LTC4300-2, the part also waits for VCC2 to rise above 2V. This ensures that the part does not try to function until it has enough voltage to do so.
PAGE 9
LTC4300-1/LTC4300-2 Operation resistors and 100pF equivalent capacitance on both sides of the part. By comparison with Figure 2, the VCC = 3.3V curve shows that increasing the capacitance from 50pF to 150pF results in a tPHL increase from 55ns to 75ns. Larger output capacitances translate to longer delays (up to 150ns). Users must quantify the difference in propagation times for a rising edge vs a falling edge in their systems and adjust setup and hold times accordingly.
PAGE 10
LTC4300-1/LTC4300-2 Applications Information Resistor Pull-Up Value Selection The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25V/µs on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value R using the formula: R ≤ (VCC(MIN) – 0.6) (800,000) / C where R is the pull-up resistor value in ohms, VCC(MIN) is the minimum VCC voltage and C is the equivalent bus capacitance in picofarads (pF).
PAGE 11
LTC4300-1/LTC4300-2 Applications Information associated with hot swapping have settled. Owing to their small capacitance, the SDAIN and SCLIN pins cause minimal disturbance on the backplane busses when they make contact with the connector. Figure 6 shows the LTC4300-2 in a CompactPCI configuration. The LTC4300-2 receives its VCC voltage from one of the long “early power” pins.
PAGE 12
LTC4300-1/LTC4300-2 Applications Information VCC R1 10k BD_SEL SDA STAGGERED CONNECTOR SCL R2 10k BACKPLANE CONNECTOR STAGGERED CONNECTOR BACKPLANE I/O PERIPHERAL CARD 1 POWER SUPPLY Hot Swap C1 0.01µF ENABLE SDAIN SCLIN R4 10k R5 10k R6 10k VCC SDAOUT CARD_SDA LTC4300-1 U1 SCLOUT CARD_SCL GND READY I/O PERIPHERAL CARD 2 POWER SUPPLY Hot Swap C3 0.
PAGE 13
LTC4300-1/LTC4300-2 Applications Information VCC2 BD_SEL VCC SDA SCL R2 10k STAGGERED CONNECTOR R1 10k BACKPLANE CONNECTOR STAGGERED CONNECTOR BACKPLANE I/O PERIPHERAL CARD 1 POWER SUPPLY Hot Swap 5.1Ω C1 0.01µF R6 10k VCC2 SDAOUT CARD_SDA SCLOUT CARD_SCL SCLIN ACC GND C2 0.01µF I/O PERIPHERAL CARD 2 POWER SUPPLY Hot Swap 5.1Ω R5 10k LTC4300-2 U1 VCC SDAIN R4 10k C3 0.
PAGE 14
LTC4300-1/LTC4300-2 Applications Information BACKPLANE BACKPLANE CONNECTOR I/O PERIPHERAL CARD 1 VCC R1 10k R2 10k C1 0.01µF R3 100k ENABLE SDAIN SDA SCLIN SCL R5 10k R6 10k VCC SDAOUT CARD_SDA LTC4300-1 U1 SCLOUT CARD_SCL GND C2 0.1µF R4 10k READY I/O PERIPHERAL CARD 2 C3 0.01µF R7 100k ENABLE SDAIN SCLIN C4 0.
PAGE 15
LTC4300-1/LTC4300-2 Applications Information 2-WIRE SYSTEM 2 2-WIRE SYSTEM 1 VCC = 5V VCC C1 0.01µF R1 10k R4 10k C2 0.01µF R5 10k LTC4300-1 VCC R2 R3 5.1k 5.1k R6 10k R7 10k LTC4300-1 VCC R8 10k ENABLE SDAOUT SDAOUT ENABLE SDA1 SDAIN SCLOUT SCLOUT SDAIN SDA1 SCL1 TO OTHER SYSTEM 1 DEVICES SCLIN READY READY SCLIN SCL1 TO OTHER SYSTEM 2 DEVICES GND LONG DISTANCE BUS NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURE 4 GND 430012 F09 Figure 9.
PAGE 16
LTC4300-1/LTC4300-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev G) 0.889 ±0.127 (.035 ±.005) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ±.0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.
PAGE 17
LTC4300-1/LTC4300-2 Revision History REV DATE DESCRIPTION A 09/12 Added TPHL,SKEW parameter to Electrical Characteristics PAGE NUMBER Updated format B 04/14 3 1-18 Updated MS8 Package Drawing 16 430012fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaof itsinformation circuits as described herein will not infringe on existing patent rights.
PAGE 18
LTC4300-1/LTC4300-2 Typical Application RDROP VCC R1 10k VCC_LOW C2 0.01µF R2 10k R3 10k SDAIN SCL SCLIN R5 10k VCC SDAOUT SDA2 LTC4300-1 U1 SCLOUT SCL2 ENABLE SDA R4 10k GND READY 430012 F10 NOTE: APPLICATION ASSUMES BUS CAPACITANCES WITHIN “PROPER OPERATION” REGION OF FIGURES 3 AND 4 Figure 10. System with Disparate VCC Voltages VCC 5V R1 10k C2 0.01µF R4 10k SDAIN SCL SCLIN SCL C1 0.