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LTC4300A-1/LTC4300A-2

4300a12fa

TYPICAL APPLICATION

FEATURES DESCRIPTION

Hot Swappable

2-Wire Bus Buffers

The LTC

4300A series hot swappable 2-wire bus buffers

allow I/O card insertion into a live backplane without corrup-

tion of the data and clock busses. When the connection is

made, the LTC4300A-1/LTC4300A-2 provide bidirectional

buffering, keeping the backplane and card capacitances

isolated. Rise-time accelerator circuitry* allows the use of

weaker DC pull-up currents while still meeting rise-time

requirements. During insertion, the SDA and SCL lines are

precharged to 1V to minimize bus disturbances.

The LTC4300A-1 incorporates a CMOS threshold digital

ENABLE input pin, which forces the part into a low current

mode when driven to ground and sets normal operation

when driven to V

. It also includes an open drain READY

output pin, which indicates that the backplane and card

sides are connected together. The LTC4300A-2 replaces

the ENABLE pin with a dedicated supply voltage pin, V

CC2

for the card side, providing level shifting between 3.3V

and 5V systems. Both the backplane and card may be

powered with supply voltages ranging from 2.7V to 5.5V,

with no constraints on which supply voltage is higher. The

LTC4300A-2 also replaces the READY pin with a digital

CMOS input pin, ACC, which enables and disables the

rise-time accelerator currents.

The LTC4300A is available in a small 8-pin MSOP package.

Input–Output Connection t

PLH

APPLICATIONS

Bidirectional Buffer for SDA and SCL Lines

Increases Fanout

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal from Backplane

Isolates Input SDA and SCL Lines from Output

Compatible with I

C, I

C Fast Mode and SMBus

Standards (Up to 400kHz Operation)

Low I

Chip Disable: <1μA (LTC4300A-1)

READY Open Drain Output (LTC4300A-1)

1V Precharge on all SDA and SCL Lines

Supports Clock Stretching, Arbitration and

Synchronization

5V to 3.3V Level Translation (LTC4300A-2)

High Impedance SDA, SCL Pins for V

= 0V

Small MSOP 8-Pin Package

Hot Board Insertion

Servers

Capacitance Buffer/Bus Extender

Desktop Computer

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot

Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are

the property of their respective owners. *Protected by U.S. Patents, including 6650174.

10k

3.3V

10k

ENABLE

SCLIN SCLOUT

SDAIN SDAOUT

GND

LTC4300A-1

READY

0.01μF

4300a12 TA01

10k

OUTPUT

SIDE

50pF

INPUT

SIDE

150pF

4300a12 TA02

Summary of content (16 pages)

PAGE 1
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffers FEATURES DESCRIPTION n The LTC®4300A series hot swappable 2-wire bus buffers allow I/O card insertion into a live backplane without corruption of the data and clock busses. When the connection is made, the LTC4300A-1/LTC4300A-2 provide bidirectional buffering, keeping the backplane and card capacitances isolated. Rise-time accelerator circuitry* allows the use of weaker DC pull-up currents while still meeting rise-time requirements.
PAGE 2
LTC4300A-1/LTC4300A-2 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW VCC to GND .................................................... –0.3 to 7V VCC2 to GND (LTC4300A-2)............................ –0.3 to 7V SDAIN, SCLIN, SDAOUT, SCLOUT.................. –0.3 to 7V READY, ENABLE (LTC4300A-1) ...................... –0.3 to 7V ACC (LTC4300A-2) ......................................... –0.3 to 7V Operating Temperature Range LTC4300A-1C/LTC4300A-2C ....................
PAGE 3
LTC4300A-1/LTC4300A-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
PAGE 4
LTC4300A-1/LTC4300A-2 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 3: The connection circuitry always regulates its output to a higher voltage than its input.
PAGE 5
LTC4300A-1/LTC4300A-2 PIN FUNCTIONS ENABLE/VCC2 (Pin 1): Chip Enable Pin/Card Supply Voltage. For the LTC4300A-1, this is a digital CMOS threshold input pin. Grounding this pin puts the part in a low current (<1μA) mode. It also disables the rise-time accelerators, disables the bus precharge circuitry, drives READY low, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. Drive ENABLE all the way to VCC for normal operation. Connect ENABLE to VCC if this feature is not being used.
PAGE 6
LTC4300A-1/LTC4300A-2 BLOCK DIAGRAM (LTC4300A-1) 2-Wire Bus Buffer and Hot Swap™ Controller 2mA 2mA SLEW RATE DETECTOR SLEW RATE DETECTOR 8 VCC BACKPLANE-TO-CARD CONNECTION SDAIN 6 CONNECT 74 SDAOUT CONNECT CONNECT ENABLE 100k RCH1 100k RCH3 1V PRECHARGE 100k RCH2 100k RCH4 2mA 2mA SLEW RATE DETECTOR SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION SCLIN 3 CONNECT 2 SCLOUT + CONNECT – VCC – 1V + + – – STOP BIT AND BUS IDLE 0.5μA + 0.55VCC/ 0.
PAGE 7
LTC4300A-1/LTC4300A-2 BLOCK DIAGRAM (LTC4300A-2) 2-Wire Bus Buffer and Hot Swap Controller VCC 8 2mA 2mA SLEW RATE DETECTOR ACC 1 VCC2 SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION SDAIN 6 74 SDAOUT CONNECT CONNECT 100k RCH1 CONNECT 100k RCH3 1V PRECHARGE 100k RCH2 100k RCH4 2mA 2mA SLEW RATE DETECTOR ACC SLEW RATE DETECTOR 5 ACC BACKPLANE-TO-CARD CONNECTION SCLIN 3 CONNECT 2 SCLOUT + CONNECT – + + – – VCC2 – 1V STOP BIT AND BUS IDLE 0.5μA + 0.55VCC/ 0.
PAGE 8
LTC4300A-1/LTC4300A-2 OPERATION Start-Up When the LTC4300A first receives power on its VCC pin, either during power-up or during live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above 2.5V. For the LTC4300A-2, the part also waits for VCC2 to rise above 2V. This ensures that the part does not try to function until it has enough voltage to do so.
PAGE 9
LTC4300A-1/LTC4300A-2 OPERATION OUTPUT SIDE 50pF INPUT SIDE 150pF INPUT SIDE 150pF 4300a12 F01 OUTPUT SIDE 50pF 4300a12 F02 Figure 1. Input–Output Connection t PLH Figure 2. Input–Output Connection t PHL supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows tPHL as a function of temperature and voltage for 10k pull-up resistors and 100pF equivalent capacitance on both sides of the part.
PAGE 10
LTC4300A-1/LTC4300A-2 APPLICATIONS INFORMATION Resistor Pull-Up Value Selection The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25V/μs on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value R using the formula: R ≤ (VCC(MIN) – 0.
PAGE 11
LTC4300A-1/LTC4300A-2 APPLICATIONS INFORMATION these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making riseand fall-time requirements difficult to meet. Placing a LTC4300A on the edge of each card, however, isolates the card capacitance from the backplane.
PAGE 12
LTC4300A-1/LTC4300A-2 APPLICATIONS INFORMATION the figure. In addition, make sure that the VCC bypassing on the backplane is large compared to the 0.01μF bypass capacitor on the card. Establishing early power VCC ensures that the 1V precharge voltage is present at the SDAIN and SCLIN pins before they make contact. Connect VCC2 to the output of one of the CompactPCI power supply Hot Swap circuits. VCC2 is monitored by a filtered UVLO circuit.
PAGE 13
LTC4300A-1/LTC4300A-2 APPLICATIONS INFORMATION BACKPLANE CONNECTOR BACKPLANE I/O PERIPHERAL CARD 1 R1 10k STAGGERED CONNECTOR VCC2 R2 10k VCC SDA SCL C1 0.01μF VCC SDAIN SCLIN R5 10k R6 10k VCC2 SDAOUT CARD_SDA U1 LTC4300A-2 SCLOUT CARD_SCL ACC GND C2 0.01μF R4 10k STAGGERED CONNECTOR I/O PERIPHERAL CARD 2 C3 0.01μF VCC SDAIN SCLIN C4 0.01μF R8 10k R9 10k R10 10k VCC2 SDAOUT CARD2_SDA U2 LTC4300A-2 SCLOUT CARD2_SCL ACC GND t t t 4300a12 F06 Figure 6.
PAGE 14
LTC4300A-1/LTC4300A-2 APPLICATIONS INFORMATION rise- and fall-time specifications for 1nF of capacitance, thus allowing much more interconnect distance. In this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed VOL specification with respect to the ground at the other end.
PAGE 15
LTC4300A-1/LTC4300A-2 REVISION HISTORY REV DATE DESCRIPTION A 7/12 Added TPHL,SKEW parameter to Electrical Characteristics PAGE NUMBER 3 4300a12fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 16
LTC4300A-1/LTC4300A-2 TYPICAL APPLICATIONS RDROP VCC (LTC4300A) VCC (BUS) R1 10k C2 0.01μF R2 10k R3 10k SDAIN SCL SCLIN R5 10k VCC SDAOUT SDA2 U1 LTC4300A-1 SCLOUT SCL2 ENABLE SDA R4 10k READY GND 4300a12 F08 Figure 8. System with Disparate VCC Voltages VCC 5V R1 10k C2 0.01μF R4 10k SDA SCL C1 0.01μF SDAIN VCC VCC2 SDAOUT SCLIN U1 LTC4300A-2 SCLOUT GND CARD_VCC, 3.3V R3 10k R2 10k CARD_SDA CARD_SCL ACC 4300a12 F09 Figure 9. 5V to 3.