Datasheet

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LTC4300A-3

4300a3fa

Typical applicaTion

FeaTures DescripTion

Level-Shifting

Hot Swappable 2-Wire

Bus Buffer with Enable

The LT C

4300A-3 hot swappable 2-wire bus buffer allows

I/O card insertion into a live backplane without corruption

of the data and clock busses. When the connection is made,

the LTC4300A-3 provides bidirectional buffering, keeping

the backplane and card capacitances isolated. Rise time

accelerator circuitry allows the use of weaker DC pull-up

currents while still meeting rise time requirements. During

insertion, the SDA and SCL lines are precharged to 1V to

minimize bus disturbances.

The LTC4300A-3 provides level translation between

3.3V and 5V supplies. The backplane and card can both

be powered with supplies ranging from 2.7V to 5.5V.

The LTC4300A-3 also incorporates a CMOS threshold

ENABLE pin which forces the part into a low current mode

and isolates the card from the backplane. When driven to

, the ENABLE pin sets normal operation.

The LTC4300A-3 is available in the MSOP and 3mm × 3mm

DFN packages.

Input–Output Connection

applicaTions

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal From Backplane

Logic Threshold ENABLE Input

Isolates Input SDA and SCL Lines From Output

Compatible with I

C, I

C Fast Mode and SMBus

Standards (Up to 400kHz Operation)

1V Precharge on all SDA and SCL Lines

Supports Clock Stretching, Arbitration and

Synchronization

■

5V to 3.3V Level Translation

■

High Impedance SDA, SCL Pins for V

= 0V,

CC2

= 0V

■

Small 8-Lead DFN and MSOP Packages

Hot Board Insertion

Servers

Capacitance Buffer/Bus Extender

Desktop Computer

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners. *Patent pending.

3.3V

10k10k

ENABLE

SCLIN SCLOUT

SDAIN SDAOUT

6 7

3 2

8 1

GND

LTC4300A-3

0.01µF

CC2

4300a3 TA01

10k 10k

OFF ON

200ns/DIV

OUTPUT

SIDE

50pF

0.5V/DIV

4300a3 TA01b

INPUT

SIDE

150pF

Summary of content (14 pages)

PAGE 1
LTC4300A-3 Level-Shifting Hot Swappable 2-Wire Bus Buffer with Enable Features n n n n n n n ■ ■ ■ Description Bidirectional Buffer* for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal From Backplane Logic Threshold ENABLE Input Isolates Input SDA and SCL Lines From Output Compatible with I2C, I2C Fast Mode and SMBus Standards (Up to 400kHz Operation) 1V Precharge on all SDA and SCL Lines Supports Clock Stretching, Arbitration and Synchroniza
PAGE 2
LTC4300A-3 Absolute Maximum Ratings (Note 1) VCC to GND...................................................– 0.3V to 7V VCC2 to GND.................................................. –0.3V to 7V SDAIN, SCLIN, SDAOUT, SCLOUT................. –0.3V to 7V ENABLE......................................................... –0.3V to 7V Operating Temperature Range LTC4300A-3C.......................................... 0°C to 70°C LTC4300A-3I........................................
PAGE 3
LTC4300A-3 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VCC Positive Supply Voltage l 2.7 l 2.7 5.5 VCC2 Card Side Supply Voltage ISD Supply Current in Shutdown Mode VENABLE = 0V 20 IVCC1 VCC Supply Current VSDAIN = VSCLIN = 0V, VCC1 = VCC2 = 5.
PAGE 4
LTC4300A-3 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 3: The connection circuitry always regulates its output to a higher voltage than its input.
PAGE 5
LTC4300A-3 Pin Functions (DFN/MSOP) VCC2 (Pin 1): Card Supply Voltage. This is the supply voltage for the devices on the card I2C busses. Connect pull-up resistors from SDAOUT and SCLOUT to this pin. Place a bypass capacitor of at least 0.01µF close to this pin for best results. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to the SCL bus on the card. SCLIN (Pin 3): Serial Clock Input. Connect this pin to the SCL bus on the backplane. GND (Pin 4): Device Ground.
PAGE 6
LTC4300A-3 Block Diagram 2-Wire Bus Buffer and Hot Swap™ Controller VCC 8 2mA 2mA SLEW RATE DETECTOR 1 VCC2 SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION SDAIN 6 CONNECT 74 SDAOUT CONNECT CONNECT 100k 100k 1V PRECHARGE 100k 100k 2mA 2mA SLEW RATE DETECTOR SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION SCLIN 3 CONNECT 2 SCLOUT + CONNECT – VCC2 – 1V + + – – STOP BIT AND BUS IDLE 0.5A + 0.55VCC/ 0.
PAGE 7
LTC4300A-3 Operation Start-Up When the LTC4300A-3 first receives power on its VCC pin, either during power-up or during live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above 2.5V. The part also waits for VCC2 to rise above 2V. This ensures that the part does not try to function until it has enough voltage to do so.
PAGE 8
LTC4300A-3 INPUT SIDE 150pF OUTPUT SIDE 50pF 0.5V/DIV OUTPUT SIDE 50pF INPUT SIDE 150pF 0.5V/DIV 200ns/DIV 4300a3 F01 200ns/DIV 4300a3 F02 Figure 1. Input–Output Connection Low to High Transition Figure 2. Input–Output Connection High to Low Transition supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus.
PAGE 9
LTC4300A-3 Applications Information Resistor Pull-Up Value Selection Live Insertion and Capacitance Buffering Application The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25V/µs on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges.
PAGE 10
LTC4300A-3 Applications Information BACKPLANE BACKPLANE CONNECTOR I/O PERIPHERAL CARD 1 VCC R7 10k SDA SCL ENA1 R8 10k STAGGERED CONNECTOR VCC2 C1 0.01µF VCC SDAIN C2 0.01µF SCLIN R1 10k R2 10k VCC2 SDAOUT CARD_SDA LTC4300A-3 SCLOUT CARD_SCL GND ENABLE R3 10k ENA2 STAGGERED CONNECTOR I/O PERIPHERAL CARD 2 C3 0.01µF VCC SDAIN C4 0.01µF SCLIN R4 10k R5 10k VCC2 SDAOUT CARD2_SDA LTC4300A-3 SCLOUT CARD2_SCL GND ENABLE R6 10k 4300A-3 F04 Figure 4.
PAGE 11
LTC4300A-3 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C) 0.70 ±0.05 3.5 ±0.05 1.65 ±0.05 2.10 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 TOP MARK (NOTE 6) 0.200 REF 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 5 0.40 ±0.10 8 1.65 ±0.
PAGE 12
LTC4300A-3 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 0.889 ±0.127 (.035 ±.005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ±.0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.
PAGE 13
LTC4300A-3 Revision History REV DATE DESCRIPTION A 09/12 Updated format of Pin Configuration and Order Information sections PAGE NUMBER 2 Added TPHL,SKEW parameter to Electrical Characteristics 3 4300a3fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 14
LTC4300A-3 Typical Application VCC 5V R1 10k C2 0.01µF R4 10k SDA SDAIN SCL SCLIN C1 0.01µF VCC VCC2 SDAOUT LTC4300A-3 SCLOUT CARD_VCC, 3.3V R3 10k R2 10k CARD_SDA CARD_SCL 4300A-3 F05 ENABLE GND Figure 5. 5V to 3.