Datasheet

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LTC4304

4304fa

Hot Swappable 2-Wire

Bus Buffer with Stuck

Bus Recovery

The LTC

4304 hot swappable 2-wire bus buffer allows I/O

card insertion into a live backplane without corruption of

the data and clock busses. When a connection is made,

the LTC4304 provides bidirectional buffering, keeping the

backplane and card capacitances isolated. If SDAOUT or

SCLOUT is low for ≥30ms (typ), the LTC4304 automatically

breaks the data and clock bus connection and

FAULT

will

pull low. At this time the LTC4304 automatically generates

up to 16 clock pulses on SCLOUT in an attempt to free the

bus. A connection will be enabled automatically when the

bus becomes free. A logic low on the ACC input enables

the LTC4304’s rise-time accelerators. A logic high on ACC

disables the rise-time accelerators, which allows SDA and

SCL bus pull-up voltages below V

During insertion, the SDA and SCL lines are precharged

to 1V to minimize bus disturbances. When driven high,

ENABLE allows the LTC4304 to connect after a stop bit or

bus idle occurs. Driving ENABLE low breaks the connection

between SDAIN and SDAOUT, SCLIN and SCLOUT. READY

is an open drain output that indicates when the backplane

and card sides are connected together.

■

Automatic Disconnect of SDA/SCL Lines when Bus

is Stuck Low for ≥30ms

■

Fault Flag for Stuck Bus

■

Recovers Stuck Busses with Automatic Clocking*

■

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

■

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal from Backplane

■

Allows Bus Pullup Voltages Above and Below V

■

±15kV Human Body Model ESD Protection

■

Isolates Input SDA and SCL Lines from Output

■

Compatible with I

, I

C Fast-Mode and SMBus

Standards (Up to 400kHz Operation)

■

READY Open Drain Output

■

1V Precharge on All SDA and SCL Lines

■

High Impedance SDA, SCL Pins for V

= 0V

■

ENABLE Gates Connection from Input to Output

■

MSOP 10-Pin and DFN (3mm × 3mm) Packages

■

Hot Board Insertion

■

Servers

■

Capacitance Buffer/Bus Extender

■

RAID Systems

CARD

100k

ENABLE

FAULT

CARD_SCL

CARD_SDA

SCLOUTSCLIN

SDAOUT

READY

SDAIN

GND

LTC4304

ACC

0.01µF

4304 TA01

10k 10k

10k10k

BACK_SCL

BACKPLANE

CONNECTOR

BACK_SDA

3.3V

STAGGERED

CONNECTOR

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6356140, 6650174, 7032051.

SDAOUT

5V/DIV

SCLOUT

5V/DIV

FAULT

5V/DIV

200 s/DIV

STUCK LOW > 30ms RECOVERS

DISCONNECT AT TIMEOUT

AUTOMATIC CLOCKING

4304 TA01b

SDAIN

5V/DIV

Stuck Bus Resolved with

Automatic Clocking

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

APPLICATIO S

Summary of content (16 pages)

PAGE 1
LTC4304 Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Automatic Disconnect of SDA/SCL Lines when Bus is Stuck Low for ≥30ms Fault Flag for Stuck Bus Recovers Stuck Busses with Automatic Clocking* Bidirectional Buffer* for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane Allows Bus Pullup Voltages Above and Below VCC ±15kV Human Body Model ESD Protection Isolates Input SD
PAGE 2
LTC4304 W W U W ABSOLUTE AXI U RATI GS (Notes 1, 2) VCC to GND .................................................. –0.3V to 7V SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE, FAULT, ACC .................................................. –0.3V to 7V Operating Temperature LTC4304C ................................................ 0°C to 70°C LTC4304I .............................................–40°C to 85°C SDAIN, SCLIN, SDAOUT, SCLOUT, FAULT READY (Note 3) .........................................
PAGE 3
LTC4304 ELECTRICAL CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN VHYS SDA, SCL, Logic Input Threshold Voltage (Note 6) Hysteresis 50 mV tPLH ENABLE Delay On-Off READY Delay Off-On VCC = 3.3V (Note 6) 300 10 ns ns tPHL ENABLE Delay Off-On READY Delay On-Off VCC = 3.
PAGE 4
LTC4304 U W TYPICAL PERFOR A CE CHARACTERISTICS ICC vs Temperature Input-Output tPHL vs Temperature 140 6.2 VCC = 5.5V 6.0 TA = 25°C unless otherwise indicated. 120 IPULLUPAC vs Temperature 14 CIN = COUT = 100pF RPULLUPIN = RPULLUPOUT = 10k 100 10 5.4 80 60 8 VCC = 3.3V 6 40 4 20 2 VCC = 2.7V 5.2 5.0 –50 IPULLUPAC (mA) tPHL (ns) ICC (mA) 5.8 5.6 VCC = 5.5V 12 –25 VCC = 2.
PAGE 5
LTC4304 U U U PI FU CTIO S ENABLE (Pin 1): Connection Enable. This is a digital threshold input pin. For normal operation ENABLE is high. Driving ENABLE below 0.8V isolates SDAIN from SDAOUT, SCLIN from SCLOUT, asserts READY low and disables automatic clocking. A rising edge on ENABLE after a fault has occurred unconditionally forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT. READY (Pin 6): Connection Status Flag.
PAGE 6
LTC4304 W BLOCK DIAGRA LTC4304 2-Wire Bus Buffer with Stuck Bus Protection 3.5mA SLEW RATE DETECTOR ACC_IN 10 VCC 3.5mA SLEW RATE DETECTOR CONNECT ACC_OUT SDAIN SDAOUT 8 200k PC_CONNECT 9 200k PC_CONNECT PRECHARGE 3.5mA 3.5mA SLEW RATE DETECTOR 200k 3 CONNECT SLEW RATE DETECTOR 200k SCLOUT SCLIN ACC_IN 2 ACC_IN 4 ACC CTRL ACC ACC_OUT + + AUTOMATIC CLOCKING – – UVLO + LOGIC PC_CONNECT – + CONNECT 1 ENABLE 7 30ms TIMER – 1.8V FAULT 1.8V READY 6 + 1.
PAGE 7
LTC4304 OPERATION Start-Up When the LTC4304 ﬁrst receives power on its VCC pin, either during power up or live insertion, it starts in an under voltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2.5V (typical). During this time, the precharge circuitry is active and forces 1V through 200K nominal resistors to the SDA and SCL pins.
PAGE 8
LTC4304 OPERATION OUTPUT SIDE 50pF 0.5V/DIV INPUT SIDE 150pF 0.5V/DIV 200ns/DIV INPUT SIDE 50pF 0.5V/DIV OUTPUT SIDE 150pF 0.5V/DIV 4303 F01 20ns/DIV Figure 1. Input-Output Connection tPLH same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 1 for a VCC = 3.3V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other).
PAGE 9
LTC4304 OPERATION A rising edge on ENABLE after a stuck bus condition has occurred forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT even if bus idle conditions are not met. At this time the internal 30ms timer is reset but not disabled. Rise Time Accelerators Once connection has been established, rise time accelerator circuits on all four SDA and SCL pins are activated (assuming accelerators are enabled, see ACC pin description).
PAGE 10
LTC4304 APPLICATIONS INFORMATION BACKPLANE VCC R1 10k BACKPLANE CONNECTOR STAGGERED CONNECTOR POWER SUPPLY HOT SWAP R2 10k I/O PERIPHERAL CARD 1 R3 10k BD_SEL CARD ENABLE/DISABLE ENABLE SDA SDAIN SCL SCLIN VCC LTC4304 C1 0.01µF R4 10k R5 10k R6 10k SDAOUT CARD1_SDA SCLOUT CARD1_SCL READY GND POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD 2 R7 10k CARD ENABLE/DISABLE ENABLE SDAIN SCLIN VCC LTC4304 C3 0.
PAGE 11
LTC4304 APPLICATIONS INFORMATION Figure 4 shows the LTC4304 in a PCI application where all of the pins have the same length. In this case, a RC ﬁlter circuit on the I/O card with a product of 10ms provides a BACKPLANE ﬁlter to prevent the LTC4304 from becoming activated until the transients associated with live insertion have settled. Connect the capacitor between ENABLE and GND, and the resistor from VCC to ENABLE. BACKPLANE CONNECTOR I/O PERIPHERAL CARD 1 VCC R1 10k R2 10k C1 0.
PAGE 12
LTC4304 APPLICATIONS INFORMATION Supply Independent Operation celerators cannot be used. Float ACC in applications where the pull-up voltage on SDAIN and SCLIN is < VCC and the pull-up voltage on SDAOUT and SCLOUT is ≥ VCC. Connect ACC to ground in applications where VCC is ≤ SDA and SCL pull-up voltages. Connect ACC to VCC for applications where SDA and SCL pull-up voltages are ≤ VCC.
PAGE 13
LTC4304 APPLICATIONS INFORMATION VCC SHELF MANAGER R1 10k VCC ShMC R2 10k C1 0.01µF ENABLE R3 2.7k ATCA BOARD C2 0.01µF R4 2.7k VCC SDAIN SDAOUT LTC4304 SCLOUT SCLIN R6 10k VCC ENABLE VCC SDAOUT LTC4304 SCLOUT SCLIN IPMC SDAIN IPM BUS (1 OF 2) R5 10k 4304 F06 Figure 6.
PAGE 14
LTC4304 U PACKAGE DESCRIPTIO DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.38 0.10 10 0.675 0.05 3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES) 3.00 0.10 (4 SIDES) PACKAGE OUTLINE 1.65 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD10) DFN 1103 5 0.200 REF 0.25 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.25 0.05 0.50 BSC 0.75 0.05 0.50 BSC 2.38 0.05 (2 SIDES) 1 0.00 – 0.05 2.38 0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1.
PAGE 15
LTC4304 U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 0.127 (.035 .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 0.102 (.118 .004) (NOTE 3) 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) DETAIL “A” 0.497 0.076 (.0196 .003) REF 0 – 6 TYP GAUGE PLANE 1 2 3 4 5 0.53 0.152 (.021 .006) DETAIL “A” 0.86 (.034) REF 1.10 (.043) MAX 0.18 (.
PAGE 16
LTC4304 U TYPICAL APPLICATIO 5V 3.3V C1 0.01µF R1 10k R4 10k VCC R2 10k R5 10k LTC4304 SCLIN SCLOUT BACK_SCL CARD_SCL SDAIN SDAOUT BACK_SDA CARD_SDA READY FAULT FROM MICROPROCESSOR ENABLE R3 10k BACKPLANE CONNECTOR STAGGERED CONNECTOR GND ACC 4304 F07 CARD Figure 7.