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LTC4305

4305f

APPLICATIO S

TYPICAL APPLICATIO

FEATURES

DESCRIPTIO

The LTC

4305 is a 2-channel, 2-wire bus multiplexer with

bus buffers to provide capacitive isolation between the

upstream bus and downstream buses. Through software

control, the LTC4305 connects the upstream 2-wire bus

to any desired combination of downstream channels.

Each channel can be pulled up to a supply voltage ranging

from 2.2V to 5.5V, independent of the LTC4305 supply

voltage. The downstream channels are also provided with

an ALERT1–ALERT2 inputs for fault reporting.

Programmable timeout circuitry disconnects the down-

stream buses if the bus is stuck low. When activated, rise

time accelerators source currents into the 2-wire bus pins

to reduce rise time. Driving the ENABLE pin low restores

all features to their default states. Three address pins

provide 27 distinct addresses.

The LTC4305 is available in 16-lead (4mm × 5mm) DFN

and SSOP packages.

■

Nested Addressing

■

5V/3.3V Level Translator

■

Capacitance Buffer/Bus Extender

■

1:2 2-Wire Multiplexer/Switch

■

Connect SDA and SCL Lines with 2-Wire Bus

Commands

■

Supply Independent Bidirectional Buffer for SDA

and SCL Lines Increases Fan-Out

■

Programmable Disconnect from Stuck Bus

■

Compatible with I

C and SMBus Standards

■

Rise Time Accelerator Circuitry

■

SMBus Compatible ALERT Response Protocol

■

Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

■

±10kV Human Body Model ESD Ruggedness

■

16-Lead (4mm × 5mm) DFN and SSOP Packages

2-Channel,

2-Wire Bus Multiplexer with

Capacitance Buffering

, LTC and LT are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Patent Pending.

A Level-Shifting and Nested Addressing Application

10k

0.01µF

10k 10k10k 10k10k

ADDRESS = 1000 100

SFP

MODULE #1

10k 10k 10k

ADDRESS = 1111 000

MICRO-

CONTROLLER

SFP

MODULE #2

ADDRESS = 1111 000

2.5V

3.3V

4305 TA01

SCLIN

SDAIN

ALERT

ADR2

ADR1

ADR0

GND

SCL1

SDA1

ALERT1

SCL2

SDA2

ALERT2

LTC4305

4305 TA01b

= 3.3V

VCARD1 = 3.3V

VCARD2 = 5V

VBACK = 2.5V

SCL2

2V/DIV

500ns/DIV

SCL1

2V/DIV

SCLIN

2V/DIV

C Bus Waveforms

Summary of content (20 pages)

PAGE 1
LTC4305 2-Channel, 2-Wire Bus Multiplexer with Capacitance Buffering U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 1:2 2-Wire Multiplexer/Switch Connect SDA and SCL Lines with 2-Wire Bus Commands Supply Independent Bidirectional Buffer for SDA and SCL Lines Increases Fan-Out Programmable Disconnect from Stuck Bus Compatible with I2C and SMBus Standards Rise Time Accelerator Circuitry SMBus Compatible ALERT Response Protocol Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backp
PAGE 2
LTC4305 W W U W ABSOLUTE AXI U RATI GS (Note 1) Supply Voltage (VCC) ................................... –0.3V to 7V Input Voltages (ADR0, ADR1, ADR2, ENABLE, ALERT1, ALERT2) .................... –0.3V to 7V Output Voltages (ALERT, READY) ............... –0.3V to 7V Input/Output Voltages (SDAIN, SCLIN, SCL1, SDA1, SCL2, SDA2) ...................... –0.3V to 7V Output Sink Current (SDAIN, SCLIN, SCL1, SDA1, SCL2, SDA2, ALERT, READY) ............... 10mA Operating Temperature Range LTC4305C ...........
PAGE 3
LTC4305 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 0.8 1.0 1.
PAGE 4
LTC4305 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C Interface 0.75 • VCC 0.9 • VCC ● VADR(H) ADR0–2 Input High Voltage VADR(L) ADR0–2 Input Low Voltage IADR(IN, L) ADR0–2 Logic Low Input Current ADR0–2 = 0V, VCC = 5.
PAGE 5
LTC4305 U W TYPICAL PERFOR A CE CHARACTERISTICS Buffer Circuitry tPHL vs Temperature Rise Time vs CBUS vs VCC 120 250 100 dV = 0.3V • VCC TO 0.7V • VCC RBUS = 10k VCC = 5V 5 VCC = 5V 60 40 VCC = 3.3V CURRENT (mA) RISE TIME (ns) 80 VCC = 5V 150 100 50 20 VCC = 3.
PAGE 6
LTC4305 U U U PI FU CTIO S ALERT1–ALERT2 (Pins 14, 1): Fault Alert Inputs, Channels 1–2. Devices on each of the two output channels can pull their respective pin low to indicate that a fault has occurred. The LTC4305 then pulls the ALERT low to pass the fault indication on to the host. See the “Operation” section below for the details of how ALERT is set and cleared. Connect unused fault alert inputs to VCC. ALERT (Pin 2): Fault Alert Output.
PAGE 7
LTC4305 W BLOCK DIAGRA INACC UPSTREAM DOWNSTREAM BUFFERS SLEW RATE DETECTOR OUTACC SLEW RATE DETECTOR 13 SDA1 SDAIN 3 15 SDA2 INACC UPSTREAM DOWNSTREAM BUFFERS SLEW RATE DETECTOR OUT ACC 2 DOWNSTREAM 1V THRESHOLD COMPARATORS SLEW RATE DETECTOR 12 SCL1 SCLIN 5 STUCK LOW 0.52V COMPARATORS 16 SCL2 READY 11 FET1 FET2 CONN ALERT 1V THRESHOLD COMPARATORS FET1 SCLIN 1.6V/1.
PAGE 8
LTC4305 U OPERATIO Control Register Bit Definitions Register 1 (01h) Register 0 (00h) BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION d7 Downstream Connected R Indicates if upstream bus is connected to any downstream buses 0 = upstream bus disconnected from all downstream buses 1 = upstream bus connected to one or more downstream buses d7 Upstream Accelerators Enable R/W Activates upstream rise time accelerator currents 0 = upstream rise time accelerator currents inactive (default) 1 = ups
PAGE 9
LTC4305 U OPERATIO Register 3 (03h) Register 2 (02h) BIT NAME TYPE* DESCRIPTION d7 Reserved R Not Used d6 Reserved R Not Used d5 Connection Requirement R/W Sets logic requirements for downstream buses to be connected to upstream bus 0 = Bus Logic State bits (see register 3) of buses to be connected must be high for connection to occur (default) 1 = Connect regardless of downstream logic state d4 Reserved R d3 Reserved R BIT NAME TYPE* DESCRIPTION d7 Bus 1 FET State R/W Sets and indicates
PAGE 10
LTC4305 U OPERATIO The LTC4305 is a 2-channel 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Masters on the upstream 2-wire bus (SDAIN and SCLIN) can command the LTC4305 to neither, either or both of the 2 downstream buses. Masters can also program the LTC4305 to disconnect the upstream bus from the downstream buses if the bus is stuck low.
PAGE 11
LTC4305 U OPERATIO separated by the series combination of their switches’ on resistances. While neither, either or both downstream buses may be connected at the same time, logic high levels are corrupted if both downstream buses are active and both the VCC voltage and one downstream bus pull-up voltage are larger than the pull-up supply voltage of the other downstream bus. An example of this issue is shown in Figure 1.
PAGE 12
LTC4305 U OPERATIO disconnects the downstream buses from the upstream bus by de-biasing the Upstream-Downstream Buffers. Note that the downstream switches remain in their existing state. The Timeout Real Time bit of register 0 indicates the real-time status of the stuck low situation. The Latched Timeout Bit of register 0 is a latched bit that is set high when a timeout occurs.
PAGE 13
LTC4305 U OPERATIO regardless of their individual address settings. The mass write can be masked by setting the mass write enable bit of register 2 to zero. Address (0001 100) is the SMBus Alert Response Address. Figure 3 shows data transfer over a 2-wire bus. Glitch Filters The LTC4305 provides glitch filters on the SDAIN and SCLIN pins as required by the I2C Fast Mode (400kHz) Specification.
PAGE 14
LTC4305 U OPERATIO Table 1.
PAGE 15
LTC4305 U W U U APPLICATIO S I FOR ATIO For larger bus capacitances, refer to equation (1) below. The LTC4305 works with capacitive loads up to 2nF. Design Example A typical LTC4305 application circuit is shown in Figure 5. The circuit illustrates the level-shifting, multiplexer/switch and capacitance buffering features of the LTC4305. In this application, the LTC4305 VCC voltage and downstream bus 1 are powered from 3.3V, downstream bus 2 is powered from 5V, and the upstream bus is powered from 2.
PAGE 16
LTC4305 U U W U APPLICATIO S I FOR ATIO Level Shifting Considerations In Figure 5, the LTC4305 VCC voltage is less than or equal to both of the downstream bus pull-up voltages, so both downstream buses can be active at the same time. Likewise, the rise time accelerators can be turned on for the downstream buses, but must never be activated on SCLIN and SDAIN, because doing so would result in significant current flow from VCC to VBACK during rising edges.
PAGE 17
LTC4305 U W U U APPLICATIO S I FOR ATIO VCC C1 0.01µF R1 10k R2 10k 7 VCC 5 MICROCONTROLLER 3 VCC 6 SCLIN ALERT1 R3 10k R7 10k CARD_SCL1 13 CARD_SDA1 14 CARD_ALERT1# VBUS2 ENABLE SCL2 2 R6 10k SDAIN R4 200k VCC SCL1 SDA1 R5 10k 12 SDA2 ALERT ALERT2 R8 10k 16 R9 10k R10 10k CARD_SCL2 15 CARD_SDA2 1 CARD_ALERT2# LTC4305 VCC 10 9 OPEN 8 4 ADR2 READY 11 R11 10k ADR1 ADR0 GND 4305 F07 BACKPLANE BACKPLANE CONNECTOR CARD CONNECTOR ADDRESS = 1010 000 Figure 7.
PAGE 18
LTC4305 U PACKAGE DESCRIPTIO DHD Package 16-Lead Plastic DFN (4mm x 5mm) (Reference LTC DWG # 05-08-1707) 0.70 ±0.05 4.50 ±0.05 3.10 ±0.05 2.44 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 4.34 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5.00 ±0.10 (2 SIDES) R = 0.20 TYP 4.00 ±0.10 (2 SIDES) 9 0.40 ± 0.10 16 2.44 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH (DHD16) DFN 0504 8 0.200 REF 1 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 0.00 – 0.05 4.34 ±0.
PAGE 19
LTC4305 U PACKAGE DESCRIPTIO GN Package 16-Lead Narrow Plastic SSOP (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .0532 – .0688 (1.35 – 1.75) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.
PAGE 20
LTC4305 U TYPICAL APPLICATIO VCC C1 0.01µF R1 10k R2 10k R3 10k R4 10k R5 10k R6 10k R7 10k VCC SCLIN SDAIN MICROCONTROLLER SCL1 ENABLE TEMPERATURE SENSOR SDA1 ALERT1 ALERT READY LTC4305 VCC2 VCC R8 10k ADR2 OPEN ADR1 ADR0 R9 10k R10 10k SCL2 VOLTAGE MONITOR SDA2 ALERT2 I/O CARD GND 4305 F08 ADDRESS = 1010 000 Figure 8.