typically 60mV. This offset is nearly independent of pull-up
current. (See Typical Performance curves.)
Propagation Delays
During a rising edge, the rise time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 2 for V
= 5.5V and a 10k pull-up resistor on each side (50pF
on one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective propagation delay is negative.
There is a fi nite propagation delay through the connec-
tion circuitry for falling waveforms. Figure 3 shows the
falling edge waveforms for the same pull-up resistors and
equivalent capacitance conditions as used in Figure 2. An
external N-channel MOSFET device pulls down the voltage
on the side with 150pF capacitance; LTC4309 pulls down
the voltage on the opposite side, with a delay of 85ns. This
delay is always positive and is a function of supply voltage,
temperature and the pull-up resistors and equivalent bus
capacitances on both sides of the bus.
The Typical Performance Characteristics section shows
Propagation Delay as a function of temperature and voltage
for 2.7k pull-up resistors and 50pF equivalent capacitance
on both sides of the part. Also, the Propagation Delay as
a function of Output Capacitance curve shows that larger
output capacitances translate to longer delays. Users must
quantify the difference in propagation times for a rising
edge versus a falling edge in their systems and adjust
setup and hold times accordingly.
Bus Stuck Low Timeout
When SDAOUT or SCLOUT is low, an internal timer is
started. The timer is only reset by the respective pin
going high. If the bus stuck low does not go high within
30ms (typical), the FAULT pin pulls low indicating a bus
stuck low condition. If DISCEN is connected to V
, the
connection circuitry is disabled, breaking the connection
between the respective input and output pins. In addition,
after at least 40μs, up to 16 clock pulses at 8.5kHz (typi-
cal) is generated on the SCLOUT pin by the LTC4309 in an
attempt to free the stuck low bus. Once the clock pulses
have completed, a stop bit is generated on the SCLOUT
and SDAOUT pins to reset all devices on the bus.
If the stuck low SDAOUT or SCLOUT recovers to a logic
high, the FAULT flag clears, and the LTC4309 waits for
either a stop bit or a bus idle condition to activate the
connection circuitry to reconnect the input and output
If DISCEN is connected to GND, the FAULT pin will pull
low, but the connection circuitry will not be disabled,
leaving the input and output busses connected. Also, no
clock or stop bit is generated.
When powering up into a bus stuck low condition, the
connection circuitry connecting the SDA and SCL busses
on the I/O card with those on the backplane is not activated.
30ms after UVLO, the FAULT pin pulls low indicating a bus
stuck low condition and automatic clocking and stop bit
generation takes place as described above.
READY Digital Output
This pin provides a digital fl ag which is low when either
ENABLE is low, the start-up sequence described earlier
in this section has not been completed, or the LTC4309
Figure 2. Input-Output Rising Edge Waveforms
Figure 3. Input-Output Falling Edge Waveforms
4307 F01
4307 F02