Datasheet

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LTC4309

4309fa

The LTC

4309 hot swappable 2-wire bus buffer allows

I/O card insertion into a live backplane without corrup-

tion of the data and clock busses. The LTC4309 provides

bidirectional buffering, keeping the backplane and card

capacitances isolated. Low offset and high V

tolerance

allows cascading of multiple devices on the clock and data

busses. If SDAOUT or SCLOUT are low for 30ms, FAULT

will pull low indicating a stuck bus low condition. If DISCEN

is tied high, the LTC4309 will automatically break the bus

connection and generate up to 16 clock pulses and a stop

bit in an attempt to free the bus. A connection will resume

if the stuck bus is cleared. If DISCEN is connected to GND,

the busses will remain connected with no clock or stop

bit generation. ACC input enables rise-time accelerators

for high capacitively loaded busses.

During insertion, the SDA and SCL lines are precharged to

1V to minimize bus disturbances. When driven high, the

ENABLE input allows the LTC4309 to connect after a stop

bit or bus idle. Driving ENABLE low breaks the connection

between SDAIN and SDAOUT, SCLIN and SCLOUT. READY

is an open drain output which indicates that the backplane

and card sides are connected.

Level Shifting Low Offset Hot

Swappable 2-Wire Bus Buffer

with Stuck Bus Recovery

Live Board Insertion

Servers

Capacitance Buffer/Bus Extender

RAID Systems

ATCA

Bidirectional Buffer Increases Fanout

60mV Buffer Offset Independent of Load

Optional Disconnect when Bus is Stuck Low

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal from Backplane

Level Shift 2.5V, 3.3V and 5V Busses

Compatible with Non-Compliant V

C Devices

±6kV Human Body Model ESD Ruggedness

Isolates Input SDA and SCL Lines from Output

Compatible with I

C™, I

C Fast-Mode and SMBus

READY Open Drain Output

FAULT Open Drain Output

1V Precharge on All SDA and SCL Lines

Optional Rise Time Accelerators

High Impedance SDA, SCL Pins for V

= 0

Available in Small 12-Pin DFN (4mm x 3mm) and

16-Lead SSOP Packages

Rising Edge from Asserted Low

4309 TA01

ENABLEEN

SCLIN

SDAIN

SCL1

SDA1

FAULT

ACC

GND

SCLOUT

SDAOUT

SCL2

SDA2

LTC4309

READY

3.3V

10k

10k 10k

2.7k 2.7k

10k

ENABLE

CC2

SCLIN

CARD

CONNECTOR

BACKPLANE

CONNECTOR

SDAIN

FAULT

ACC

GND

SCLOUT

SDAOUT

LTC4309

READY

10k

100k

10k 10k

0.01μF

10k

FAULT FAULT

DISCENDISCEN

100ns/DIV

200mV/DIV

200

400

600

800

1000

100

200 300 400

4309 G01

500 600

SDAOUT

SDAIN

LOW

OFFSET

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents including

6356140, 6650174, 7032051.

Summary of content (16 pages)

PAGE 1
LTC4309 Level Shifting Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery DESCRIPTION FEATURES n n n n n n n n n n n n n n n The LTC®4309 hot swappable 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. The LTC4309 provides bidirectional buffering, keeping the backplane and card capacitances isolated. Low offset and high VOL tolerance allows cascading of multiple devices on the clock and data busses.
PAGE 2
LTC4309 ABSOLUTE MAXIMUM RATINGS (Note 1, 6) VCC, VCC2 to GND ............................................–0.3 to 6V SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE, FAULT, ACC, DISCEN .......................–0.3 to 6V Maximum Sink Current (SDA, SCL, FAULT, READY) ISINK ......................................................................50mA Operating Temperature LTC4309C ................................................ 0°C to 70°C LTC4309I..............................................
PAGE 3
LTC4309 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER VCC Positive Supply Voltage CONDITIONS MIN TYP MAX UNITS VCC2 Input Side Accelerator Supply Voltage ICC VCC Input Supply Current Enabled VCC = VCC2 = 5.5V, VSDAIN = VSCLIN = 0V (Note 2) l ISD VCC Input Supply Current Disabled VCC = VCC2 = 5.5V, SDA = SCL = 5.
PAGE 4
LTC4309 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 3.3V, VCC2 = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VTHR(HYST) (Note 3) ILEAK SDA, SCL Logic Input Threshold Voltage Hysteresis Digital Input Capacitance SDAIN, SDAOUT, SCLIN, SCLOUT Input Leakage Current SDA, SCL, ACC, DISCEN Pins l VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, Driven SDA/SCL = 0.
PAGE 5
LTC4309 TYPICAL PERFORMANCE CHARACTERISTICS ICC Enabled Current vs Temperature ICC Disabled Current vs Temperature 8 ICC2 Enabled Current vs Temperature 220 20 7 6.5 VCC = 3.3V 6 VCC = 2.3V –25 VCC = 5.5V 12 VCC = 3.3V 8 4 5.5 5 –50 200 16 VCC = 5.5V SUPPLY CURRENT (MA) 7.5 IPULLUPAC (mA) ICC ENABLED CURRENT (mA) TA = 25°C, VCC = 3.3V, VCC2 = 3.3V unless otherwise noted. 0 50 25 TEMPERATURE (oC) 75 –25 25 50 0 TEMPERATURE (°C) 75 4309 G02 130 PROPAGATION DELAY (ns) 110 VCC = 2.
PAGE 6
LTC4309 PIN FUNCTIONS (DE12/GN16) ENABLE (Pin 1/Pin1): Connection Enable Input. This 1.4V digital threshold input pin enables or disables the LTC4309. For normal operation pull or connect ENABLE high. Driving ENABLE below the 0.8V threshold isolates SDAIN from SDAOUT, SCLIN from SCLOUT, asserts READY low, and prohibits automatic clock and stop bit generation during a fault condition. A rising edge on ENABLE after a fault has occurred forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT.
PAGE 7
LTC4309 PIN FUNCTIONS (DE12/GN16) VCC (Pin 12/Pin 16): Supply Voltage Input. Bypass this pin to GND with a capacitor of at least 0.01μF and place close to VCC for best results. EXPOSED PAD (Pin 13 DE12 Package Only): Exposed Pad may be left open or connected to device ground.
PAGE 8
LTC4309 OPERATION Start-Up When the LTC4309 ﬁrst receives power on its VCC pin, either during power up or live insertion, it starts in an under voltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2V. This ensures the LTC4309 does not try to function until enough supply voltage is present. During this time, the 1V precharge circuitry is actively forcing 1V through 100k nominal resistors to the SDA and SCL pins.
PAGE 9
LTC4309 OPERATION OUTPUT SIDE 50pF 1V/DIV INPUT SIDE 150pF 1V/DIV 200ns/DIV INPUT SIDE 150pF 1V/DIV 4307 F01 Figure 2. Input-Output Rising Edge Waveforms typically 60mV. This offset is nearly independent of pull-up current. (See Typical Performance curves.) Propagation Delays During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent capacitance on the line.
PAGE 10
LTC4309 OPERATION has disconnected the input and output busses due to a bus stuck low condition. READY goes high when ENABLE is high and start-up is complete. The pin is driven by an open drain pull-down device capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor to the bus pull-up supply to provide the pull-up. FAULT Digital Output This pin provides a digital flag which is low when SDA or SCL is low for 30ms (typical).
PAGE 11
LTC4309 APPLICATIONS INFORMATION to the pull-up impedance, multiple LTC4309 buffers can be used in a single system. This allows the user to divide the line and device capacitances into more sections with buffering and meet rise and fall times. The LTC4309 disconnects when both bus I/O’s are above 0.48V and rising. In systems with large ground bounce, if many devices are cascaded, the 0.48V threshold can be exceeded, and the transients associated with the ground bounce can appear to be a rising edge.
PAGE 12
LTC4309 APPLICATIONS INFORMATION BACKPLANE CONNECTOR BACKPLANE VCC CARD CONNECTORS I/O PERIPHERAL CARD 1 C1 0.01μF C2 0.01μF VCC2 R1 10k R2 10k R3 10k R4 10k VCC2 SDA SDAIN SCL SCLIN FAULT FAULT READY READY ENABLE ENA1 R7 10k VCC LTC4309 R5 10k R6 10k DISCEN SDAOUT CARD 1_SDA SCLOUT CARD 1_SCL ACC GND I/O PERIPHERAL CARD N C3 0.01μF C4 0.
PAGE 13
LTC4309 APPLICATIONS INFORMATION BACKPLANE CONNECTOR CARD CONNECTORS BACKPLANE I/O PERIPHERAL CARD 1 VCC C1 0.01μF C2 0.01μF VCC2 R1 10k R2 10k R3 10k R4 10k VCC VCC2 SDA SDAIN SCL SCLIN FAULT FAULT READY READY R6 10k DISCEN LTC4309 SDAOUT CARD 1_SDA SCLOUT CARD 1_SCL ACC ENABLE ENA1 R5 10k GND R7 10k I/O PERIPHERAL CARD N C3 0.01μF C4 0.
PAGE 14
LTC4309 APPLICATIONS INFORMATION VCC VCC R1 2.7k R2 2.7k R3 10k R4 10k C1 0.01MF C2 0.01MF C3 0.01MF R5 2.7k VCC VCC2 R6 2.7k C4 0.01MF R7 10k R8 10k R9 2.7k R10 2.7k R11 10k R12 10k C5 0.01MF VCC2 VCC C6 0.01MF DISCEN DISCEN ENABLE ENABLE ENABLE READY READY FAULT FAULT LTC4309 LTC4309 LTC4309 FAULT SDA1 SDAOUT SDAIN SDAIN SDAOUT SDAOUT SDAIN SCL1 SCLOUT SCLIN SCLOUT SCLOUT SCLIN ACC GND R14 2.7k VCC VCC2 DISCEN READY R13 2.
PAGE 15
LTC4309 PACKAGE DESCRIPTION DE/UE Package 12-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1695) 0.70 p0.05 3.60 p0.05 1.70 p0.05 2.20 p0.05 (2 SIDES) PACKAGE OUTLINE 0.25 p 0.05 3.30 p0.05 (2 SIDES) 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 p0.10 (2 SIDES) 7 0.40 p 0.10 R = 0.115 TYP 12 R = 0.05 TYP 3.00 p0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 1.70 p 0.05 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER 6 0.25 p 0.05 0.75 p0.05 0.200 REF 1 3.30 p0.
PAGE 16
LTC4309 TYPICAL APPLICATION 5V to 3.3V Level Translator 3.3V 5V C1 0.01MF R1 10k C2 0.