Datasheet

LTC4312
17
4312f
APPLICATIONS INFORMATION
Level Translating to Bus Voltages < 2.25V
The LTC4312 can be used for level translation to bus volt-
ages below 2.25V if certain conditions are met. In order
to perform this level translation, RTAs on the low voltage
side need to be disabled in order to prevent an over drive
of the low voltage bus. If one of the output channels is
pulled up to the low voltage bus supply, the other output
channel needs to be disabled when this channel is active,
in order to prevent cross conduction between the output
channels. Since the buffer turn-on and turn-off voltages
are 0.3•V
MIN
, the minimum bus supply voltage is deter-
mined by equation 5:
V
DD,BUS(MIN)
≥
0.3 • V
MIN
0.7
(5)
in order to meet the V
IH
= 0.7• V
DD,BUS
requirement and
not impact the high side noise margin. Users willing to live
with a lower logic high noise margin can level translate
down to 1.5V. An example of voltage level translation from
3.3V to 1.8V is illustrated in Figure 11, where a 3.3V input
voltage level is translated to a 1.8V output voltage level on
channel 1. Tying V
CC
to 3.3V satisfi es equation 5. Ground-
ing V
CC2
disables the RTA on the low voltage channel.
V
MIN
defaults to V
CC
under these conditions, making the
buffer turn off voltage 0.99V. Channel 2 must be disabled
when channel 1 is enabled. A similar voltage translation
can also be performed going from a 3.3V bus supply on
the output side to a 1.8V bus supply on the input side if
ACC is tied high to disable the input RTA and if V
CC
and
V
CC2
are tied to the output side bus supply.
Figure 11. Level Shifting Down to 1.8V Using the LTC4312, V
CC2
Is Grounded to Disable the Rise Time Accelerator
on the Low Voltage Bus. ENABLE2 Must Be Low Whenever ENABLE1 Is High
LTC4312
GND
V
CC
V
CC2
4312 F11
SCLOUT1
SDAOUT1
SCLOUT2
SDAOUT2
SCLOUT1
SDAOUT1
SCLOUT2
SDAOUT2
SCLIN
SDAIN
ENABLE1
ENABLE2
ACC
DISCEN
FAULT
3.3V
R2
10k
R1
10k
SCLIN
SDAIN
ENABLE1
ENABLE2
C1
0.01μF
3.3V 1.8V
R5
10k
R4
10k
C2
0.01μF
C3
0.01μF
5V
R7
10k
R6
10k
R3
10k