Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsInterface ICsInterface IC - buffer amplifiers, accelerators I²C hot swap 400 kHz MSOP 8

LTC4313-1/LTC4313-2/

LTC4313-3

4313123f

Typical applicaTion

FeaTures DescripTion

2-Wire Bus Buffers with

High Noise Margin

The LTC

4313 is a hot swappable 2-wire bus buffer

that provides bidirectional buffering while maintain-

ing a low offset voltage and high noise margin up to

0.3 • V

. The high noise margin allows the LTC4313 to be

interoperable with devices that drive a high V

(>0.4V) and

allows multiple LTC4313s to be cascaded. The LTC4313-1

and LTC4313-2 support level translation between 3.3V and

5V busses. In addition to these voltages, the LTC4313-3

also supports level translation to 1.5V, 1.8V and 2.5V.

During insertion, the SDA and SCL lines are pre-charged to

1V to minimize bus disturbances. Connection is established

between the input and output after ENABLE is asserted

high and a stop bit or bus idle condition has been detected

on the SDA and SCL pins.

If both data and clock are not simultaneously high at least

once in 45ms, the input is disconnected from the output.

Up to 16 clock pulses are subsequently generated to free

the stuck bus. Rise time accelerators (RTAs) provide pull-up

currents on SDA and SCL rising edges to meet rise time

specifications in heavily loaded systems. The RTAs are

configured as slew limited switches in the LTC4313-1 and

2.5mA current sources in the LTC4313-2. The LTC4313-3

does not have RTAs.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 6356140, 6650174,

7032051, 7478286.

400kHz Operation

applicaTions

Bidirectional Buffer Increases Fanout

High Noise Margin with V

= 0.3 • V

Compatible with Non-Compliant I

C Devices That

Drive a High V

Strong (LTC4313-1) and 2.5mA (LTC4313-2)

Rise Time Accelerator Current

Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses

Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

Stuck Bus Disconnect and Recovery

Compatible with I

C, I

C Fast Mode and SMBus

±4kV Human Body Model ESD Ruggedness

High Impedance SDA, SCL Pins When Unpowered

8-Lead MSOP and 8-Lead (3mm × 3mm) DFN

Packages

Capacitance Buffers/Bus Extender

Live Board Insertion

Telecommunications Systems Including ATCA

Level Translation

PMBus

Servers

LTC4313-1

GND

4313123 TA01a

READY

SCLOUT

SDAOUT

ENABLE

SCLIN

SDAIN

SCL1

SDA1

2.7k2.7k

0.01µF

3.3V

READY

SCL2

SDA2

1.3k10k

1.3k

1V/DIV

500ns/DIV

4313123 TA01b

BUS_IN

= 2.7kΩ, C

BUS_IN

= 50pF

BUS_OUT

= 1.3kΩ, C

BUS_OUT

= 100pF

SCLOUT

SCLIN

Summary of content (20 pages)

PAGE 1
LTC4313-1/LTC4313-2/ LTC4313-3 2-Wire Bus Buffers with High Noise Margin Features n n n n n n n n n n n Description Bidirectional Buffer Increases Fanout High Noise Margin with VIL = 0.3•VCC Compatible with Non-Compliant I2C Devices That Drive a High VOL Strong (LTC4313-1) and 2.5mA (LTC4313-2) Rise Time Accelerator Current Level Shift 1.5V, 1.8V, 2.5V, 3.
PAGE 2
LTC4313-1/LTC4313-2/ LTC4313-3 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage VCC....................................... –0.3V to 6V Input Voltage ENABLE................................... –0.3V to 6V Input/Output Voltages SDAIN, SDAOUT, SCLIN, SCLOUT............................................ –0.3V to 6V Output Voltage READY.................................. –0.3V to 6V Output Sink Current READY....................................50mA Operating Ambient Temperature Range LTC4313C...................
PAGE 3
LTC4313-1/LTC4313-2/ LTC4313-3 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
PAGE 4
LTC4313-1/LTC4313-2/ LTC4313-3 Typical Performance Characteristics ICC Enabled Current vs Supply Voltage 9.0 ICC Disabled Current vs Supply Voltage 4.0 VSDAIN,SCLIN = 0V VENABLE = 5.5V 8.5 TA = 25°C, VCC = 3.3V unless otherwise noted. 12 VSDAIN,SCLIN = 0V VENABLE = 0V 11 IOL (mA) ICC (mA) ICC (mA) 3.0 7.0 9 8 VSDA,SCL = 0.4V 7 6 2.5 6.5 6.0 VSDA,SCL = 0.6V 10 3.5 8.0 7.5 Buffer DC IOL vs Temperature 5 2 3 2.5 3.5 4 4.5 5 5.5 VCC (V) 2.0 6 2.5 3 3.5 4 4.5 5 5.
PAGE 5
LTC4313-1/LTC4313-2/ LTC4313-3 Pin Functions ENABLE (Pin 1): Connection Enable Input. When driven low, the ENABLE pin isolates SDAIN and SCLIN from SDAOUT and SCLOUT, asserts READY low, disables rise time accelerators and inhibits automatic clock and stop bit generation during a stuck low fault condition. When driven high, the ENABLE pin connects SDAIN and SCLIN to SDAOUT and SCLOUT after a stop bit or bus idle has been detected on both busses.
PAGE 6
LTC4313-1/LTC4313-2/ LTC4313-3 Block Diagram * VCC 200k 200k IRTA 200k PRECHARGE VCC 200k PRECHARGE CONNECT * IRTA PRECHARGE CONNECT SCLIN SCLOUT VCC SLEW RATE DETECTOR 0.2V/µs * SLEW RATE DETECTOR 0.2V/µs VCC * CONNECT IRTA IRTA SDAIN SDAOUT SLEW RATE DETECTOR 0.2V/µs SLEW RATE DETECTOR 0.2V/µs RTA_SCLOUT_EN RTA_SCLIN_EN RTA_SDAIN_EN I2C Hot Swap LOGIC I2C Hot Swap LOGIC LOGIC + – VIL = 0.33 • VCC – UVLO – READY 95µs TIMER CONNECT + 1.4V/1.3V VIL = 0.
PAGE 7
LTC4313-1/LTC4313-2/ LTC4313-3 Operation The LTC4313 is a high noise margin bus buffer which provides capacitance buffering for I2C signals. Capacitance buffering is achieved by using back to back buffers on the clock and data channels which isolate the SDAIN and SCLIN capacitances from the SDAOUT and SCLOUT capacitances respectively. All SDA and SCL pins are fully bidirectional.
PAGE 8
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information The LTC4313 provides capacitance buffering, data and clock Hot Swap capability and level translation. The high noise margin of the LTC4313 permits interoperability with I2C devices that drive a high VOL permits series connection of multiple LTC4313s and improves I2C communication reliability. The LTC4313 isolates backplane and card capacitances and provides slew control of falling edges while level translating 3.3V and 5V busses.
PAGE 9
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information Input to Output Offset Voltage of the LTC4313-1 and LTC4313-2 must be greater than or equal to 0.9•VCC. An example is shown in Figure 3 where the input bus voltage is greater than VCC. During a rising edge, the input bus rise rate will be accelerated by the RTA up to a voltage of 2.97V after which the bus rise rate will reduce to a value that is determined by the bus current and bus capacitance.
PAGE 10
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information Falling Edge Characteristics The LTC4313 introduces a propagation delay on falling edges due to the finite response time and the finite current sink capability of the buffers. In addition the LTC4313 also slew limits the falling edge to an edge rate of 45V/µs (typ). The slew limited falling edge eliminates fast transitions on the busses and minimizes transmission line effects in systems.
PAGE 11
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information Live Insertion and Capacitance Buffering Application Figure 5 illustrates an application of the LTC4313 that takes advantage of the LTC4313’s Hot Swap, capacitance buffering and precharge features. If the I/O cards were plugged directly into the backplane without LTC4313 buffers, all of the backplane and card capacitances would directly add together, making rise time requirements difficult to meet.
PAGE 12
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information BACKPLANE CARD CONNECTOR CONNECTOR I/O PERIPHERAL CARD 1 5V C1 0.01µF 3.3V R1 10k R2 10k C2 0.01µF R3 10k VCC R4 10k LTC4313 R5 10k READY READY SCL SCLIN SCLOUT CARD 1_SCL SDA SDAIN SDAOUT CARD 1_SDA ENABLE ENABLE 1 R6 10k GND ••• I/O PERIPHERAL CARD N ••• C3 0.01µF C4 0.01µF VCC R7 10k LTC4313 R8 10k READY ENABLE N SCLIN SCLOUT CARD N_SCL SDAIN SDAOUT CARD N_SDA ENABLE R9 10k GND 4313123 F05 Figure 5.
PAGE 13
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information Telecommunications Systems The LTC4313 has several features that make it an excellent choice for use in telecommunication systems such as ATCA. Referring to Figures 7 and 8, buffers are used on the edges of the field replaceable units (FRU) and shelf managers to shield devices on these cards from the large backplane capacitance.
PAGE 14
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information The LTC4313-2 on only one of the shelf managers is enabled at any given time. The hot insertion logic on the LTC4313-3 allows the FRUs to be plugged or unplugged from a live backplane. The features mentioned previously provide noise immunity and allow timing specifications to be met for a wide range of backplane loading conditions.
PAGE 15
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information First, when two or more buffers are connected in a cascade configuration, if the sum of the offsets across the cascade (refer to Equation 3 and the data sheets of the corresponding buffers) plus the worst-case driven logic low voltage exceeds the minimum buffer turn-off voltage, signals will not be propagated across the cascade. The maximum driven logic low voltage must be set accordingly, for correct operation in such cascades.
PAGE 16
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information I/O CARD #2-4 I/O CARD #1 5V 3.3V VCC C1 0.01µF SCL1 R1 5k R2 2.7k VCC LTC4313-1 SCLIN LTC4300A SCLOUT GND SCLIN SCL2 R3 2.7k SCL3 SCLOUT GND * CB2 690pF CB1 100pF VCC LTC4307 SCLIN * PARASITIC BACKPLANE CAPACITANCE SCLOUT GND R4 5k SCL4 BACKPLANE I/O CARD #5 4313123 F09 Figure 9. The LTC4313-1 Operating in a Cascade with Other LTC Buffers with Active RTAs.
PAGE 17
LTC4313-1/LTC4313-2/ LTC4313-3 Applications Information 10000 100 M=1 2 0 1000 M=1 M=3 10 CBUS (pF) CBUS (pF) 1000 M=2 4 6 RBUS (kΩ) 8 100 10 2 0 4 6 RBUS (kΩ) 4313123 F11 Figure 12. Recommended Maximum R1 and CB1 Values for the LTC4313 Operating with Multiple LTC4307s in a 3.3V System 3.3V R1 10k 10 4313123 F12 Figure 11. Recommended Maximum R1 and CB1 Values for the LTC4313 Operating with Multiple LTC4300As in a 3.3V System C1 0.
PAGE 18
LTC4313-1/LTC4313-2/ LTC4313-3 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD8 Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C) 0.70 ±0.05 3.5 ±0.05 1.65 ±0.05 2.10 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 TOP MARK (NOTE 6) 0.200 REF 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 5 0.
PAGE 19
LTC4313-1/LTC4313-2/ LTC4313-3 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 0.254 (.010) 7 6 5 0.52 (.0205) REF 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 3.20 – 3.45 (.126 – .136) 0.53 ± 0.152 (.021 ± .
PAGE 20
LTC4313-1/LTC4313-2/ LTC4313-3 Typical Application Cascaded Application with Level Shifting and Operation with a Non-Compliant I2C Device 3.3V 2.5V R1 10k R2 10k R3 10k VCC ENABLE 5V R4 10k C1 0.01µF R5 10k VCC ENABLE READY LTC4313-3 R6 10k R7 10k READY LTC4313-2 SCL1 SCLIN SCLOUT SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDAIN SDAOUT SDA2 BACKPLANE OR LONG CABLE RUN GND GND NON-COMPLIANT I2C DEVICE VOL = 0.