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Table Of Contents

LTC4315

4315f

TYPICAL APPLICATION

FEATURES DESCRIPTION

2-Wire Bus Buffer with

High Noise Margin

The LTC4315 is a hot-swappable 2-wire bus buffer

that provides bidirectional buffering, while maintain-

ing a low offset voltage and high noise margin up to

0.3 • V

. The high noise margin allows the LTC4315 to be

interoperable with devices that drive a high V

(>0.4V)

and allows multiple LTC4315s to be cascaded. The LTC4315

supports level translation between 1.5V, 1.8V, 2.5V, 3.3V

and 5V busses.

During insertion, the SDA and SCL lines are precharged to

1V t o m i n i m i z e b u s d i s t u r b a n c e s . C o n n e c t i o n i s e s t a b l i s h e d

between the input and output after ENABLE is asserted

high and a stop bit or bus idle condition has been detected

on the SDA and SCL pins.

If both data and clock are not simultaneously high at

least once in 45ms and DISCEN is high, a FAUL T signal

is generated indicating a stuck bus low condition and the

input is disconnected from the output. Up to 16 clock

pulses are subsequently generated to free the stuck bus.

A three state ACC pin enables input and output side rise

time accelerators of various strengths.

400kHz Operation

APPLICATIONS

Bidirectional Buffer Increases Fanout

High Noise Margin with V

= 0.3 • V

Compatible with Non-Compliant I

C Devices That

Drive a High V

Selectable Rise Time Accelerator Current

Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses

Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

Stuck Bus Disconnect and Recovery

Compatible with I

C, I

C Fast Mode and SMBus

±4kV Human Body Model ESD Ruggedness

High Impedance SDA, SCL pins When Unpowered

12-Lead (4mm × 3mm) DFN and 12-Lead MSOP

Packages

Capacitance Buffers/Bus Extender

Live Board Insertion

Telecommunications Systems Including ATCA

Level Translation

PMBus

Servers

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. patents, including 6356140, 6650174, 7032051, 7478286.

LTC4315

GND

CC2

4315 TA01a

READY

SCLOUT

SDAOUT

FAULT

DISCEN

ENABLE

SCLIN

SDAIN

ACC

SCL1

SDA1

2.7k2.7k0.01µF

3.3V

READY

SCL2

SDA2

FAULT

1.3k10k

10k1.3k

1V/DIV

500ns/DIV

4315 TA01b

SCLIN

SCLOUT

BUS_IN

= 2.7k, C

BUS_IN

= 50pF

BUS_OUT

= 1.3k, C

BUS_OUT

= 400pF, ACC = 0V

Summary of content (20 pages)

PAGE 1
LTC4315 2-Wire Bus Buffer with High Noise Margin FEATURES DESCRIPTION n The LTC4315 is a hot-swappable 2-wire bus buffer that provides bidirectional buffering, while maintaining a low offset voltage and high noise margin up to 0.3 • VCC. The high noise margin allows the LTC4315 to be interoperable with devices that drive a high VOL (>0.4V) and allows multiple LTC4315s to be cascaded. The LTC4315 supports level translation between 1.5V, 1.8V, 2.5V, 3.3V and 5V busses.
PAGE 2
LTC4315 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltages VCC, VCC2 ........................... –0.3V to 6V Input Voltages ACC, DISCEN, ENABLE ......... –0.3V to 6V Input/Output Voltages SDAIN, SCLIN, SCLOUT, SDAOUT ....................................................... –0.3V to 6V Output Voltages FAULT, READY ................... –0.3V to 6V Output Sink Currents FAULT, READY ...................................................50mA Operating Ambient Temperature Range LTC4315C ..........................
PAGE 3
LTC4315 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 5.5 V Power Supply/Start-Up l VCC Input Supply Voltage VDD,BUS 2-Wire Bus Supply Voltage VCC2 Output Side Accelerator Supply Voltage ICC Input Supply Current VENABLE = VCC = VCC2 = 5.
PAGE 4
LTC4315 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP IACC(IN, Z) Allowable Leakage Current in the Open State VCC = VCC2 = 5V l ±5 μA VREADY(OL) READY Output Low Voltage IREADY = 3mA, VCC = 5V l 0.4 V IREADY(OH) READY Off Leakage Current VCC = VREADY = 5V l ±5 μA 0.
PAGE 5
LTC4315 TYPICAL PERFORMANCE CHARACTERISTICS ICC Enabled Current vs Supply Voltage TA = 25°C, VCC = VCC2 = 3.3V unless otherwise noted. ICC Disabled Current vs Supply Voltage 9.0 ICC2 Enabled Current vs Supply Voltage 4.0 0.4 VSDAIN,SCLIN = 0V VENABLE = 5.5V 8.5 VSDAIN,SCLIN = 0V VENABLE = 0V VSDAIN,SCLIN = 0V VENABLE = 5.5V 3.5 7.5 ICC2 (mA) 0.3 ICC (mA) ICC (mA) 8.0 3.0 7.0 0.2 2.5 6.5 6.0 2 3 2.5 4 3.5 4.5 5 5.5 2.0 6 2 2.5 3 VCC (V) 3.5 4 4.5 5 5.5 0.
PAGE 6
LTC4315 PIN FUNCTIONS ACC (Pin 5): Three-State Acceleration Strength Selector. This pin controls the current strength of the rise time accelerators on both the input and output sides. Rise time accelerators (RTAs) are disabled if ACC is high, in current source mode if ACC is open and in the slew limited switch mode if ACC is low. See Table 1 in the Applications Information section. Grounding VCC2 selectively disables the output side RTAs independent of the ACC setting.
PAGE 7
LTC4315 BLOCK DIAGRAM 200k VCC 200k IRTA 200k PRECHARGE VCC2 200k PRECHARGE CONNECT IRTA PRECHARGE CONNECT SCLIN SCLOUT VCC SLEW RATE DETECTOR 0.2V/μs IRTA VCC2 SLEW RATE DETECTOR 0.2V/μs IRTA CONNECT SDAIN SDAOUT SLEW RATE DETECTOR 0.2V/μs SLEW RATE DETECTOR 0.
PAGE 8
LTC4315 OPERATION The Block Diagram shows the major functional blocks of the LTC4315. The LTC4315 is a high noise margin bus buffer which provides capacitance buffering for I2C signals. Capacitance buffering is achieved by using back to back buffers on the clock and data channels, which isolate the SDAIN and SCLIN capacitances from the SDAOUT and SCLOUT capacitances respectively. All SDA and SCL pins are fully bidirectional.
PAGE 9
LTC4315 APPLICATIONS INFORMATION The LTC4315 provides capacitance buffering, data and clock Hot Swap capability and level translation of I2C signals on its clock and data pins. The high noise margin of the LTC4315 permits interoperability with I2C devices that drive a high VOL, permits series connection of multiple LTC4315s and provides improved I2C communication reliability.
PAGE 10
LTC4315 APPLICATIONS INFORMATION If VCC2 is tied low, output RTAs are disabled independent of the state of the ACC pin. Using a combination of the ACC pin and the VCC2 voltage, the input and output side RTAs can be controlled independently. The RTAs are also internally disabled during power up, VCC2 transitions described in the Operation section and during a bus stuck low event. The RTAs when activated pull the bus up to 0.9 • VCC and 0.9 • VCC2 on the input and output sides of the SDA and SCL pins.
PAGE 11
LTC4315 APPLICATIONS INFORMATION INPUT TO OUTPUT OFFSET VOLTAGE STUCK BUS DISCONNECT AND RECOVERY While propagating a logic low voltage on its SDA and SCL pins, the LTC4315 introduces a positive offset voltage between the input and output. When a logic low voltage ≥200mV is driven on any of the LTC4315’s data or clock pins, the LTC4315 regulates the voltage on the opposite side to a slightly higher value.
PAGE 12
LTC4315 APPLICATIONS INFORMATION LIVE INSERTION, CAPACITANCE BUFFERING AND LEVEL TRANSLATION APPLICATION Figures 6 illustrates an application of the LTC4315 that takes advantage of the LTC4315’s Hot Swap, capacitance buffering and level translation features. If the I/O cards were plugged directly into the backplane without LTC4315 buffers, all of the backplane and card capacitances would directly add together, making rise time requirements difficult to meet.
PAGE 13
LTC4315 APPLICATIONS INFORMATION In Figure 6, a staggered connector is used to connect the LTC4315 to the backplane. VCC and GND are the longest pins to ensure that the LTC4315 is powered and forcing a 1V precharge voltage on the medium length SDA and SCL pins before they contact the backplane. The 1V precharge voltage is applied to the SDA and SCL pins through 200k resistors.
PAGE 14
LTC4315 APPLICATIONS INFORMATION TELECOMMUNICATIONS SYSTEMS The LTC4315 has several features that make it an excellent choice for use in telecommunications systems such as ATCA. Referring to Figures 8 and 9, buffers are used on the edges of the field replaceable units (FRUs) and shelf managers to shield devices on these cards from the large backplane capacitance. The input capacitance of the LTC4315 is less than the 10pF maximum specification for buffers used in bussed ATCA applications.
PAGE 15
LTC4315 APPLICATIONS INFORMATION from a live backplane. The features mentioned previously provide noise immunity and allow timing specifications to be met for a wide range of backplane loading conditions. In the 6 × 4 radial configuration shown in Figure 9, the LTC4314s on the shelf managers and the LTC4315s on the FRUs drive the large backplane capacitance while the I2C slave devices on the FRUs only drive the small input capacitance of the LTC4315.
PAGE 16
LTC4315 APPLICATIONS INFORMATION First, when two or more buffers are connected in a cascade configuration, if the sum of the offsets across the cascade (refer to Equation 3 and the data sheets of the corresponding buffers) plus the worst-case driven logic low voltage exceeds the minimum buffer turn-off voltage, signals will not be propagated across the cascade. The maximum driven logic low voltage must be set accordingly, for correct operation in such cascades.
PAGE 17
LTC4315 APPLICATIONS INFORMATION Generally, noise margin will be reduced if other RTAs turn on at a voltage less than 0.3 • VMIN. The reduction in noise margin is a function of the number of LTC4315s and the number and turn-on voltage of other RTAs, whose current must be sunk by the LTC4315 buffers. The same arguments apply for non-LTC buffer products whose RTA turn-on voltage is less than 0.3 • VMIN.
PAGE 18
LTC4315 APPLICATIONS INFORMATION The LTC4315 is interoperable with non-compliant I2C devices that drive a high VOL > 0.4V. Figure 14 shows the LTC4315 in an application where a microcontroller communicates through the LTC4315 with a non-compliant I2C device that drives a VOL of 0.6V. The LTC4313 buffers are active up to a bus voltage of 0.3 • VMIN which is 1.089V in this case, yielding a noise margin of 0.489V. 3.3V C1 0.
PAGE 19
LTC4315 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev Ø) 4.039 ± 0.102 (.159 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 12 11 10 9 8 7 0.254 (.010) 3.20 – 3.45 (.126 – .136) DETAIL “A” 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0° – 6° TYP 0.406 ± 0.076 (.016 ± .003) REF GAUGE PLANE 0.42 ± 0.038 (.0165 ± .0015) TYP 0.
PAGE 20
LTC4315 TYPICAL APPLICATION Cascaded Application with Level Shifting and Operation with a Non-Compliant I2C Device. 3.3V 2.5V R1 10k R2 10k R3 10k VCC2 VCC 5V R4 10k C1 0.01μF DISCEN VCC2 VCC R5 10k R6 10k DISCEN ENABLE ENABLE READY LTC4315 READY LTC4315 SCL1 SCLIN SCLOUT SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDAIN SDAOUT SDA2 ACC FAULT BACKPLANE OR LONG CABLE RUN GND ACC FAULT GND NON-COMPLIANT I2C DEVICE VOL = 0.