Datasheet

LTC4358
8
4358fa
APPLICATIONS INFORMATION
Figure 3. –12V Reverse Input Protection
LTC4358
GND
IN DRAIN
V
DD
OUT
V
IN
= 12V
C
LOAD
C1
0.1μF
R1
100Ω
V
OUT
12V
5A
4358 F03
MMBD1205
V
DD
Hold-Up Circuit
In the event of an input short, parasitic inductance between
the input supply of the LTC4358 and the load bypass
capacitor may cause V
DD
to glitch below its minimum
operating voltage. This causes the turn-off time (t
OFF
) to
increase. To preserve the fast turn-off time, local output
bypassing of 39μF or more is suffi cient or a 100Ω, 0.1μF
RC hold-up circuit on the V
DD
pin can be used as shown
in Figure 2a and Figure 2b.
Layout Considerations
The following advice should be considered when laying out
a printed circuit board for the LTC4358: The OUT pin should
Figure 2. Two Methods of Protecting Against Collapse
of V
DD
From Input Short and Stray Inductance
4358 F02
LTC4358
GND
IN DRAIN
V
DD
OUT
V
IN
= 12V
LTC4358
GND
IN DRAIN
V
DD
OUT
V
IN
= 12V
R1
1007
C1
0.1MF
C
BYPASS
39MF
V
OUT
V
OUT
(a)
(b)
be connected as closely as possible to the EXPOSED PAD
(drain of the MOSFET) for good accuracy. Keep the traces
to the IN and DRAIN wide and short. The PCB traces as-
sociated with the power path through the MOSFET should
have low resistance. See Figure 4.
The DRAIN acts as a heatsink to remove the heat from the
device. For a single layer PCB with the DFN package, use
Figure 5 to determine the PCB area needed for a speci-
fi ed maximum current and ambient temperature. If using
a two sided PCB, the maximum current is increased by
10%. If the FE package is used, the maximum current is
increased by 4%.