Datasheet

5
LTC485
sn 485LTC485ffs
SWITCHI G TI E WAVEFOR S
UW W
DI
3V
1.5V
t
PLH
t
r
t
SKEW
1/2 V
O
V
O
80%
10%
0V
B
A
V
O
–V
O
0V
90%
1.5V
t
PLH
t
SKEW
1/2 V
O
f = 1MHz, t
r
≤ 10ns, t
f
≤ 10ns
20%
t
f
V
DIFF
= V(A) – V(B)
LTC485 • F05
Figure 5. Driver Propagation Delays
3V
DE
A
B
DI
R
DIFF
C
L1
C
L2
RO
15pF
A
B
RE
LTC485 • F03
OUTPUT
UNDER TEST
C
L
S1
S2
V
CC
500Ω
LTC485 • F02
Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load #2
RECEIVER
OUTPUT
C
RL
15pF
1k
S1
S2
TEST POINT
V
CC
1k
LTC485 • F02
V
OD
A
B
R
R
V
OC
LTC485 • F01
Figure 1. Driver DC Test Load Figure 2. Receiver Timing Test Load
TEST CIRCUITS
PI FU CTIO S
UU U
RO (Pin 1): Receiver Output. If the receiver output is
enabled(RE low), then if A > B by 200mV, RO will be high.
If A < B by 200mV, then RO will be low.
RE (Pin 2): Receiver Output Enable. A low enables the
receiver output, RO. A high input forces the receiver
output into a high impedance state.
DE (Pin 3): Driver Outputs Enable. A high on DE enables
the driver output. A and B, and the chip will function as a
line driver. A low input will force the driver outputs into a
high impedance state and the chip will function as a line
receiver.
DI (Pin 4): Driver Input. If the driver outputs are enabled
(DE high), then a low on DI forces the outputs A low and
B high. A high on DI with the driver outputs enabled will
force A high and B low.
GND (Pin 5): Ground Connection.
A (Pin 6): Driver Output/Receiver Input.
B (Pin 7): Driver Output/Receiver Input.
V
CC
(Pin 8): Positive Supply; 4.75 < V
CC
< 5.25.