Datasheet

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LTC6945

6945f

TYPICAL APPLICATION

FEATURES DESCRIPTION

Ultralow Noise and Spurious

0.35GHz to 6GHz Integer-N

Synthesizer

The LTC

6945 is a high performance, low noise, 6GHz phase-

locked loop (PLL), including a reference divider, phase-

frequency detector (PFD) with phase-lock indicator, charge

pump, integer feedback divider and VCO output divider.

The part features a buffered, programmable VCO output

divider with a range of 1 through 6. The differential, low

noise output buffer has user-programmable output power

ranging from –6dBm to 3dBm, and may be muted through

either a digital input pin or software.

The low noise reference buffer outputs a typical 0dBm

square wave directly into a 50Ω impedance from 10MHz

to 250MHz, or may be disabled through software.

The ultralow noise charge pump contains selectable high

and low voltage clamps useful for VCO monitoring, and

also may be set to provide a V

/2 bias.

All device settings are controlled through a SPI-compatible

serial port.

LTC6945 Data Converter Sample Clock

1GHz Sample Clock Phase Noise

APPLICATIONS

Low Noise Integer-N PLL

350MHz to 6GHz VCO Input Range

–226dBc/Hz Normalized In-Band Phase Noise Floor

–274dBc/Hz Normalized In-Band 1/f Noise

–157dBc/Hz Wideband Output Phase Noise Floor

Excellent Spurious Performance

Output Divider (1 to 6, 50% Duty Cycle)

Low Noise Reference Buffer

Output Buffer Muting

Charge Pump Supply from 3.15V to 5.25V

Charge Pump Current from 250μA to 11.2mA

Configurable Status Output

SPI Compatible Serial Port Control

PLLWizard™ Software Design Tool Support

Wireless Base Stations (LTE, WiMAX, W-CDMA, PCS)

Broadband Wireless Access

Microwave Data Links

Military and Secure Radio

Test and Measurement

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

PLLWizard is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

OFFSET FREQUENCY (Hz)

–160

PHASE NOISE (dBc/Hz)

–150

–130

–110

–100

100 10k 100k 10M 40M

6945 TA01b

–170

–120

–140

–180

DSB INTEGRATION

(100Hz TO 1GHz)

RMS NOISE = 0.014°

RMS JITTER = 39fs

PFD

= 25MHz

BW = 2.3kHz

VCO

GND

–

REFO

STAT

SCLK

SDI

SDO

MUTE GND RF

–

GND

LTC6945

PFD

= 25MHz

REF

–

REF

CP V

3.3V

68nH

SAMPLE CLOCK

1GHz, 7dBm

3.3V

TUNE

432Ω

570nF

47nF

100pF

16.5Ω

CRYSTEK

CVCSO-914-1000

LOOP

BANDWIDTH

~2.3kHz

0.01μF

100pF

6945 TA01b

0.1μF

SPI BUS

470pF

1.0μF

0.01μF

51.1Ω

100MHz

REF

470pF

100pF

GND

0.1μF

100pF

50Ω

ALT SAMPLE CLOCK

500MHz OR 1GHz

3.3V

Summary of content (28 pages)

PAGE 1
LTC6945 Ultralow Noise and Spurious 0.35GHz to 6GHz Integer-N Synthesizer DESCRIPTION FEATURES n n n n n n n n n n n n n n Low Noise Integer-N PLL 350MHz to 6GHz VCO Input Range –226dBc/Hz Normalized In-Band Phase Noise Floor –274dBc/Hz Normalized In-Band 1/f Noise –157dBc/Hz Wideband Output Phase Noise Floor Excellent Spurious Performance Output Divider (1 to 6, 50% Duty Cycle) Low Noise Reference Buffer Output Buffer Muting Charge Pump Supply from 3.15V to 5.25V Charge Pump Current from 250μA to 11.
PAGE 2
LTC6945 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Supply Voltages V+ (VREF+, VREFO+, VRF+, V VCO+, VD+) to GND ......3.6V VCP+ to GND.........................................................5.5V Voltage on CP Pin .................GND – 0.3V to VCP+ + 0.3V Voltage on All Other Pins ..........GND – 0.3V to V+ + 0.3V Operating Case Temperature Range (TC) (Note 2).................................................. –40°C to 105°C Operating Junction Temperature ...........................
PAGE 3
LTC6945 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TC = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Output (REFO) fREFO Output Frequency PREFO Output Power fREFO = 10MHz, RLOAD = 50Ω l 10 250 MHz l –0.2 3.
PAGE 4
LTC6945 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TC = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to GND. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference (R) Divider All Integers Included l 1 1023 Counts All Integers Included l 32 65535 Counts High Level Input Voltage MUTE, CS, SDI, SCLK l 1.
PAGE 5
LTC6945 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TC = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless otherwise specified. All voltages are with respect to GND.
PAGE 6
LTC6945 TYPICAL PERFORMANCE CHARACTERISTICS Charge Pump Sink Current Error vs Voltage, Temperature 5 4 4 4 3 3 3 2 2 2 1 0 –1 1 0 –1 –2 –3 0 0.5 1 1.5 2 2.5 3 3.5 4 OUTPUT VOLTAGE (V) 4.5 –4 –5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 OUTPUT VOLTAGE (V) Charge Pump Source Current Error vs Voltage, Temperature 1.0 4 0.5 3 0 –2.0 –2 –2.5 –3 –3.0 –3.5 4.5 5 PVCO = 0dBm LC = 180nH CS = 270pF 105°C 25°C –40°C O=1 O=6 O=4 –55 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 7
LTC6945 TYPICAL PERFORMANCE CHARACTERISTICS VCO Input Sensitivity vs Frequency, Temperature Closed-Loop Phase Noise, fRF = 914MHz PHASE, NOISE (dBc/Hz) –20 –25 –30 105°C 25°C –40°C –35 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 FREQUENCY (GHz) –90 –100 –100 –110 –110 –120 –130 –140 RMS NOISE = 0.
PAGE 8
LTC6945 PIN FUNCTIONS VREFO+ (Pin 1): 3.15V to 3.45V Positive Supply Pin for REFO Circuitry. This pin should be bypassed directly to the ground plane using a 0.1μF ceramic capacitor as close to the pin as possible. REFO (Pin 2): Reference Frequency Output. This produces a low noise square wave, buffered from the REF± differential inputs. The output is self-biased and must be AC-coupled with a 22nF capacitor. STAT (Pin 3): Status Output.
PAGE 9
LTC6945 PIN FUNCTIONS VREF+ (Pin 26): 3.15V to 3.45V Positive Supply Pin for Reference Input Circuitry. This pin should be bypassed directly to the ground plane using a 0.1μF ceramic capacitor as close to the pin as possible. capacitors. If used single-ended, bypass REF– to GND with a 470pF capacitor. GND (Exposed Pad Pin 29): Negative Power Supply (Ground). The package exposed pad must be soldered directly to the PCB land.
PAGE 10
LTC6945 OPERATION The LTC6945 is a high performance PLL, and, combined with an external high performance VCO, can produce low noise LO signals up to 6GHz. It is able to achieve superior integrated phase noise performance due to its extremely low in-band phase noise performance. Table 1. FILT[1:0] Programming FILT[1:0] fREF 3 <20MHz 2 NA 1 20MHz to 50MHz 0 >50MHz REFERENCE INPUT BUFFER The PLL’s reference frequency is applied differentially on pins REF+ and REF–.
PAGE 11
LTC6945 OPERATION PHASE/FREQUENCY DETECTOR (PFD) The phase/frequency detector (PFD), in conjunction with the charge pump, produces source and sink current pulses proportional to the phase difference between the outputs of the R and N dividers. This action provides the necessary feedback to phase-lock the loop, forcing a phase alignment at the PFD’s inputs. The PFD may be disabled with the CPRST bit which prevents UP and DOWN pulses from being produced. See Figure 3 for a simplified schematic of the PFD.
PAGE 12
LTC6945 OPERATION CHARGE PUMP The charge pump, controlled by the PFD, forces sink (DOWN) or source (UP) current pulses onto the CP pin, which should be connected to an appropriate loop filter. See Figure 5 for a simplified schematic of the charge pump. inverting op amps in conjunction with positive-slope tuning oscillators. A passive loop filter as shown in Figure 15, used in conjunction with a positive-slope VCO, requires CPINV = 0.
PAGE 13
LTC6945 OPERATION The CPWIDE bit extends the charge pump output current pulse width by increasing the PFD reset path’s delay value (see Figure 3). CPWIDE is normally set to 0. VCO INPUT BUFFER The VCO frequency is applied differentially on pins VCO+ and VCO–. The inputs are self-biased and must be AC-coupled. Alternatively, the inputs may be used single-ended by applying the VCO frequency at VCO+ and bypassing VCO– to GND with a capacitor.
PAGE 14
LTC6945 OPERATION SERIAL PORT Single Byte Transfers The SPI-compatible serial port provides control and monitoring functionality. A configurable status output, STAT, gives additional instant monitoring. The serial port is arranged as a simple memory map, with status and control available in 12, byte-wide registers. All data bursts are comprised of at least two bytes.
PAGE 15
LTC6945 OPERATION MASTER–CS 16 CLOCKS MASTER–SCLK 7-BIT REGISTER ADDRESS MASTER–SDI LTC6945–SD0 8 BITS OF DATA A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 = WRITE Hi-Z 6945 F10 Figure 10. Serial Port Write Sequence MASTER–CS 16 CLOCKS MASTER–SCLK 7-BIT REGISTER ADDRESS MASTER–SDI 1 = READ A6 A5 A4 A3 A2 A1 A0 1 8 BITS OF DATA LTC6945–SDO Hi-Z X D7 D6 D5 D4 D3 D2 D1 D0 DX Hi-Z 6945 F11 Figure 11.
PAGE 16
LTC6945 OPERATION MASTER–CS Addr0 + Wr MASTER–SDI LTC6945–SDO Byte 0 Byte 1 Byte 2 Hi-Z 6945 F12 Figure 13. Serial Port Auto-Increment Write MASTER–CS Addr0 + Rd MASTER–SDI LTC6945–SDO Hi-Z DON’T CARE Byte 0 Byte 1 Hi-Z Byte 2 6945 F13 Figure 14. Serial Port Auto-Increment Read Serial Port Registers or expanded: The memory map of the LTC6945 may be found in Table 8, with detailed bit descriptions found in Table 9.
PAGE 17
LTC6945 OPERATION Table 8.
PAGE 18
LTC6945 APPLICATIONS INFORMATION INTRODUCTION A PLL is a complex feedback system that may conceptually be considered a frequency multiplier. The system multiplies the frequency input at REF± and outputs a higher frequency at RF±. The PFD, charge pump, N divider, and external VCO and loop filter form a feedback loop to accurately control the output frequency (see Figure 15). The R and O dividers are used to set the output frequency resolution.
PAGE 19
LTC6945 APPLICATIONS INFORMATION 4. Select loop filter components CI and CP based on BW and RZ . A reliable loop can be achieved by using the following equations for the loop capacitors (in Farads): CI = 3.5 2 • π •BW •R Z (7) 1 7 • π •BW •R Z (8) CP = LOOP FILTERS USING AN OPAMP Some VCO tune voltage ranges are greater than the LTC6945’s charge pump voltage range. An active loop filter using an op amp can increase the tuning voltage range.
PAGE 20
LTC6945 APPLICATIONS INFORMATION The next step in the algorithm is to determine the openloop bandwidth. BW should be at least 10× smaller than fPFD. Wider loop bandwidths could have lower integrated phase noise, depending on the VCO phase noise signature, while narrower bandwidths will likely have lower spurious power. Use a factor of 25 for this design: 250kHz BW = = 10kHz 25 MUTE pin held low) until programming is complete.
PAGE 21
LTC6945 APPLICATIONS INFORMATION Choosing the correct COUNTS depends upon the ratio of the bandwidth of the loop to the PFD frequency (BW/fPFD). Smaller ratios dictate larger COUNTS values. A COUNTS value of 128 will work for the ratio of 1/25. From Table 4, LKCT[1:0] = 1 for 128 counts. Using Table 5 with the previously selected ICP of 11.2mA, gives CP[3:0] = 11.
PAGE 22
LTC6945 APPLICATIONS INFORMATION OUTPUT PHASE NOISE DUE TO 1/f NOISE In-band phase noise at very low offset frequencies may be influenced by the LTC6945’s 1/f noise, depending upon fPFD.
PAGE 23
LTC6945 APPLICATIONS INFORMATION Measured RF± s-parameters are shown below in Table 11 to aid in the design of impedance matching networks. Table 11. Single-Ended RF Output Impedance FREQUENCY (MHz) IMPEDANCE (Ω) S11 (dB) Table 12. Suggested Single-Ended Matching Component Values fRF (MHz) LC (nH) CS (pF) 350 to 1500 180nH 270pF 1000 to 5800 68nH 100pF 500 102.8 – j49.7 –6.90 1000 70.2 – j60.1 –6.53 1500 52.4 – j56.2 –6.35 2000 43.6 – j49.2 –6.58 2500 37.9 – j39.6 –7.34 3000 32.
PAGE 24
LTC6945 APPLICATIONS INFORMATION and Johanson Technology, can be attractive alternatives. See Table 13 for recommended balun part numbers versus frequency range. The listed SMT baluns contain internal chokes to bias RF± and also provide input-to-output DC isolation. The pin denoted as GND or DC FEED should be connected to the VRF+ voltage. Figure 20 shows a surface mount balun’s connections with a DC FEED pin.
PAGE 25
LTC6945 APPLICATIONS INFORMATION resistance (see Figure 22 for an example). See QFN Package Users Guide, page 8, on Linear Technology website’s Packaging Information page for specific recommendations concerning land patterns and land via solder masks. Links are provided below. However, improper PCB layout can degrade the LTC6945’s inherent spurious performance. Care must be taken to prevent the reference signal fREF from coupling onto the VCO’s tune line, or into other loop filter signals.
PAGE 26
LTC6945 TYPICAL APPLICATIONS LTC6945 Wideband Frequency Hopping Local Oscillator 5V 5V 4.99k 4.99k 4.99k 4.99k 0.1μF 0.1μF 14V 0.1μF 14V 0.1μF 47μF 47μF + LT1678IS8 470pF 22nF + – + 3.3V 0.1μF 3.3V LOOP BANDWIDTH = ~7.6kHz 470pF 22nF 5V 0.1μF 274Ω 100MHz REF 3.3V 0.01μF REF– REF+ VREF+ CP VCP+ GND VREFO+ VVCO+ REFO LTC6945 STAT CS GND SCLK SPI BUS O_DIV = 2 0.1μF 12V RFMD UMS-1400-A16-G 100Ω 0.1μF 3.3V GND STAT GND CS 0.1μF GND MUTE1 3.
PAGE 27
LTC6945 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 p0.05 4.50 p 0.05 3.10 p 0.05 2.50 REF 2.65 p 0.05 3.65 p 0.05 PACKAGE OUTLINE 0.25 p0.05 0.50 BSC 3.50 REF 4.10 p 0.05 5.50 p 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p 0.10 (2 SIDES) 0.75 p 0.05 R = 0.
PAGE 28
LTC6945 TYPICAL APPLICATION LTC6945 Wideband Point-to-Point Radio Local Oscillator 5V 4.99k 4.99k 0.1μF 3.3V 11V 0.1μF 0.1μF 47μF + LT1678IS8 51.1Ω 100MHz REF 18.3nF REF– + + REF CP VCP GND VVCO+ REF VREFO+ LTC6945 STAT CS GND SCLK SDI 100Ω VTUNE –90 5V RFMD UMZ-T2-227-O16-G 4.7nF GND GND GND GND 100pF GND VCO O_DIV = 2 VD+ VCO– MUTE GND RF– RF+ VRF+ BB –100 –110 –120 –130 –140 –150 + SDO 0.1μF 230nF 3.3V 0.01μF +V REFO 3.