Datasheet

LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
14
69921234fc
operaTion
The LTC6992 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (I
SET
) and voltage (V
SET
), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
f
MASTER
=
1
t
MASTER
=1MHz • 50k •
I
SET
V
SET
A feedback loop maintains V
SET
at 1V ±30mV, leaving I
SET
as the primary means of controlling the output frequency.
The simplest way to generate I
SET
is to connect a resistor
(R
SET
) between SET and GND, such that I
SET
= V
SET
/R
SET
.
The master oscillator equation reduces to:
f
MASTER
=
1
t
MASTER
=
1MHz • 50k
R
SET
From this equation, it is clear that V
SET
drift will not affect
the output frequency when using a single program resistor
(R
SET
). Error sources are limited to R
SET
tolerance and
the inherent frequency accuracy ∆f
OUT
of the LTC6992.
R
SET
may range from 50k to 800k (equivalent to I
SET
between 1.25μA and 20μA).
The LTC6992 includes a programmable frequency divider
which can further divide the frequency by 1, 4, 16, 64,
256, 1024, 4096 or 16384 before driving the OUT pin.
The divider ratio N
DIV
is set by a resistor divider attached
to the DIV pin.
f
OUT
=
1
t
OUT
=
1MHz • 50k
N
DIV
•
I
SET
V
SET
With R
SET
in place of V
SET
/I
SET
the equation reduces to:
f
OUT
=
1
t
OUT
=
1MHz • 50k
N
DIV
• R
SET
DIVCODE
The DIV pin connects to an internal, V
+
referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6992:
1. DIVCODE determines the output frequency divider set-
ting, N
DIV
.
2. DIVCODE determines the output polarity, via the POL
bit.
V
DIV
may be generated by a resistor divider between V
+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
6992 F01
LTC6992
V
+
DIV
GND
R1
R2
2.25V TO 5.5V