Datasheet

LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
18
69921234fc
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring V
DIV
for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
t
DIVCODE
= 16 • (∆DIVCODE + 6) • t
MASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
A digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
operaTion
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
START
. The OUT pin
is held low during this time. The typical value for t
START
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of N
DIV
):
t
START(TYP)
= 500 • t
MASTER
The output will begin oscillating after t
START
. If POL = 0
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
never be less than 25% of t
OUT
.
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin volt-
ages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
track V
+
. Less than 100pF will not affect performance.
6992 F06
OUT
DIV STABLE V
DIV
V
+
t
DIVCODE
t
START
1ST PULSE WIDTH MAY BE INACCURATE
Figure 5. DIVCODE Change from 3 to 1
Figure 6. Start-Up Timing Diagram
DIV
0.5V/DIV
OUT
1V/DIV
V
+
= 3.3V
R
SET
= 200k
V
MOD
= 0.3V
100µs/DIV
6992 F05
512µs