Datasheet

LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
21
69921234fc
applicaTions inForMaTion
I
SET
Extremes (Master Oscillator Frequency Extremes)
When operating with I
SET
outside of the recommended
1.25μA to 20μA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
I
SET
< 1.25µA. At approximately 500nA, the oscillator output
will be frozen in its current state. The output could halt in
a high or low state. This avoids introducing short pulses
while frequency modulating a very low frequency output.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Pulse Width Modulation Bandwidth and Settling Time
The LTC6992 has a wide PWM bandwith, making it suitable
for a variety of feedback applications. Figure 10 shows that
the frequency response is flat for modulation frequencies
up to nearly 1/10 of the output frequency. Beyond that
point, some peaking may occur (depending on N
DIV
and
average duty cycle setting).
Duty cycle settling time depends on the master oscillator
frequency. Following a ±80mV step change in V
MOD
, the
duty cycle takes approximately eight master clock cycles
(8 • t
MASTER
) to settle to within 1% of the final value.
Examples are shown in Figures 11a and 11b.
Figure 10. PWM Frequency Response
Figure 11a. PWM Settling Time, 25% Duty Cycle Figure 11b. PWM Settling Time, 50% Duty Cycle
f
MOD
/f
OUT
(Hz/Hz)
0.001
∆D(f
MOD
)/∆D(0Hz) (dB)
10
5
–5
0
–10
–15
–20
0.01
6992 F10
10.1
÷1, 50%
÷1, 80%
÷16
÷4, 50%
÷4, 15%
V
MOD
0.1V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
V
+
= 3.3V
DIVCODE = 0
R
SET
= 200k
V
MOD
= 0.3V ±40mV
10µs/DIV
6992 F11a
V
MOD
0.1V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
V
+
= 3.3V
DIVCODE = 0
R
SET
= 200k
V
MOD
= 0.5V ±40mV
10µs/DIV
6992 F11b