Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsClock & Timing ICsDFN 6

LTC6994-1/LTC6994-2

699412fb

Typical applicaTion

FeaTures DescripTion

TimerBlox: Delay Block/

Debouncer

The LT C

6994 is a programmable delay block with a

range of 1µs to 33.6 seconds. The LTC6994 is part of

the TimerBlox

family of versatile silicon timing devices.

A single resistor, R

SET

, programs an internal master os-

cillator frequency, setting the LTC6994’s time base. The

input-to-output delay is determined by this master oscil-

lator and an internal clock divider, N

DIV

, programmable

to eight settings from 1 to 2

DELAY

DIV

•R

SET

50k

Ω

• 1µs, N

DIV

= 1, 8, 64,...,2

The output (OUT) follows the input (IN) after delaying

the rising and/or falling transitions. The LTC6994-1 will

delay the rising or falling edge. The LTC6994-2 will delay

both transitions, and adds the option to invert the output.

DEVICE DELAY FUNCTION

LTC6994-1

LTC6994-2 or

The LTC6994 also offers the ability to dynamically adjust

the delay time via a separate control voltage.

For easy configuration of the LTC6994, download the

TimerBlox Designer tool at www.linear.com/timerblox.

Noise Discriminator

applicaTions

Delay Range: 1µs to 33.6 Seconds

Configured with 1 to 3 Resistors

Delay Max Error:

– <2.3% for Delay > 512µs

– <3.4% for Delay of 8µs to 512µs

– <5.1% for Delay of 1µs to 8µs

Delay One or Both Rising/Falling Edges

2.25V to 5.5V Single Supply Operation

70µA Supply Current at 10µs Delay

500µs Start-Up Time

CMOS Output Driver Sources/Sinks 20mA

–55°C to 125°C Operating Temperature Range

Available in Low Profile (1mm) SOT-23 (ThinSOT™)

and 2mm × 3mm DFN

Noise Discriminators/Pulse Qualifiers

Delay Matching

Switch Debouncing

High Vibration, High Acceleration Environments

Portable and Battery-Powered Equipment

L, LT , LT C , LT M , Linear Technology, TimerBlox and the Linear logo are registered trademarks

and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

699412 TA01a

LTC6994-2

OUT

DIV

GND

SET

75k

3.3V

0.1µF

NOISY

INPUT

QUALIFIED

OUTPUT

2V/DIV

OUT

2V/DIV

20µs/DIV

699412 TA01b

1.5µs1.5µs

Summary of content (26 pages)

PAGE 1
LTC6994-1/LTC6994-2 TimerBlox: Delay Block/ Debouncer Features n n n n n n n n n n Description Delay Range: 1µs to 33.6 Seconds Configured with 1 to 3 Resistors Delay Max Error: – <2.3% for Delay > 512µs – <3.4% for Delay of 8µs to 512µs – <5.1% for Delay of 1µs to 8µs Delay One or Both Rising/Falling Edges 2.25V to 5.
PAGE 2
LTC6994-1/LTC6994-2 Absolute Maximum Ratings (Note 1) Supply Voltage (V+) to GND.........................................6V Maximum Voltage on Any Pin .................................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6994C.............................................–40°C to 85°C LTC6994I..............................................–40°C to 85°C LTC6994H........................................... –40°C to 125°C LTC6994MP........................................
PAGE 3
LTC6994-1/LTC6994-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER tDELAY Delay Time ∆tDELAY Delay Accuracy (Note 4) CONDITIONS MIN TYP MAX UNITS 33.55 sec ±1.7 ±2.3 ±3.0 % % ±2.4 ±3.4 ±4.4 % % ±3.8 ±5.1 ±6.
PAGE 4
LTC6994-1/LTC6994-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital I/O IN Pin Input Capacitance VIH 2.
PAGE 5
LTC6994-1/LTC6994-2 Typical Performance Characteristics V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. Delay Drift vs Temperature (NDIV ≤ 64) Delay Drift vs Temperature (NDIV ≤ 64) 1.5 1.5 RSET = 50k 3 PARTS 1.0 0.5 DRIFT (%) 0 0 –0.5 –0.5 –1.0 –1.0 –1.0 50 25 75 0 TEMPERATURE (°C) 100 –1.5 –50 –25 125 50 25 75 0 TEMPERATURE (°C) 100 699412 G01 1.5 1.5 0.5 0 0 –0.5 –0.5 –0.5 –1.0 –1.0 –1.0 50 25 75 0 TEMPERATURE (°C) 100 –1.
PAGE 6
LTC6994-1/LTC6994-2 Typical Performance Characteristics + V = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
PAGE 7
LTC6994-1/LTC6994-2 Typical Performance Characteristics V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. Typical VSET Distribution 100 50 0 0.98 0.996 1.004 VSET (V) 0.988 1.012 250 RSET = 50k, ÷1, IDLE 200 150 RSET = 100k, ÷8, ACTIVE 100 RSET = 100k, ÷8, IDLE 50 0 1.02 RSET = 50k, ÷1, ACTIVE RSET = 800k, ÷512 CLOAD = 5pF RLOAD = ∞ 2 3 Supply Current vs IN Pin Voltage 250 POWER SUPPLY CURRENT (µA) POWER SUPPLY CURRENT (µA) 150 5V IN RISING 3.3V IN RISING 3.
PAGE 8
LTC6994-1/LTC6994-2 Typical Performance Characteristics + V = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. Input Propagation Delay (tPD) vs Supply Voltage 3.0 CLOAD = 5pF 50 CLOAD = 5pF 45 20 15 10 5 OUTPUT RESISTANCE (Ω) 2.5 RISE/FALL TIME (ns) PROPAGATION DELAY (ns) 25 Output Resistance vs Supply Voltage Rise and Fall Time vs Supply Voltage 2.0 tRISE 1.5 tFALL 1.0 0.
PAGE 9
LTC6994-1/LTC6994-2 Pin Functions (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1µF capacitor. A resistor connected between SET and GND is the most accurate way to set the delay. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/°C or better temperature coefficient.
PAGE 10
LTC6994-1/LTC6994-2 Block Diagram (S6 package pin numbers shown) 5 V+ R1 4 DIV 4-BIT A/D CONVERTER POL DIGITAL FILTER R2 1 IN INPUT BUFFER MASTER OSCILLATOR V 1µs tMASTER = • SET 50kΩ ISET MCLK PROGRAMMABLE DIVIDER EDGECONTROLLED DELAY LOGIC OUTPUT OUT 6 POLARITY (LTC6994-2) ÷1, 8, 64, 512, 4096, 215, 218, 221 POR HALT OSCILLATOR IF ISET < 500nA ISET + – VSET = 1V 1V + – GND SET 3 ISET 2 699412 BD RSET 699412fb 10
PAGE 11
LTC6994-1/LTC6994-2 Operation The LTC6994 is built around a master oscillator with a 1µs minimum period. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1µs/50kΩ conversion factor that is accurate to ±1.7% under typical conditions. 1µs VSET tMASTER = • 50kΩ ISET A feedback loop maintains VSET at 1V ±30mV, leaving ISET as the primary means of controlling the input-to-output delay.
PAGE 12
LTC6994-1/LTC6994-2 Operation If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V + = For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. DIVCODE + 0.5 ± 1.5% 16 Table 1.
PAGE 13
LTC6994-1/LTC6994-2 Operation Edge-Controlled Delay The LTC6994 is a programmable delay or pulse qualifier. It can perform noise filtering, which distinguishes it from a delay line (which simply delays all input transitions). When the voltage on the LTC6994 input pin (IN) transitions low or high, the LTC6994 can delay the corresponding output transition by any time from 1µs to 33.6 seconds.
PAGE 14
LTC6994-1/LTC6994-2 Operation LTC6994-2 Functionality Figures 5 details the basic operation of the LTC6994-2 when configured for noninverting operation (POL = 0). As before, a rising edge on the IN pin initiates the timing and, if IN remains high, OUT will transition high after tDELAY . Unlike the LTC6994-1, falling edges are delayed in the same way. When IN transitions low, OUT will follow after tDELAY .
PAGE 15
LTC6994-1/LTC6994-2 Operation Changing DIVCODE After Start-Up Start-Up Time Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6994 places a priority on eliminating any “wandering” in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period.
PAGE 16
LTC6994-1/LTC6994-2 Applications Information Basic Operation The simplest and most accurate method to program the LTC6994 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a 3-step process. Alternatively, Linear Technology offers the easy-to-use TimerBlox Designer tool to quickly design any LTC6994 based circuit. Download the free TimerBlox Designer software at www.linear.com/timerblox. Step 1: Select the LTC6994 Version and POL Bit Setting.
PAGE 17
LTC6994-1/LTC6994-2 Applications Information Voltage-Controlled Delay Digital Delay Control With one additional resistor, the LTC6994 output delay can be manipulated by an external voltage. As shown in Figure 10, voltage VCTRL sources/sinks a current through RMOD to vary the ISET current, which in turn modulates the delay as described in Equation (3): The control voltage can be generated by a DAC (digital-toanalog converter), resulting in a digitally-controlled delay.
PAGE 18
LTC6994-1/LTC6994-2 Applications Information Settling Time Following a 2× or 0.5× step change in ISET , the output delay takes approximately six master clock cycles (6 • tMASTER) to settle to within 1% of the final value. An example is shown in Figure 12, using the circuit in Figure 10. VCTRL 2V/DIV Even an excellent layout will allow some coupling between IN and SET. Additional error is included in the specified accuracy for NDIV = 1 to account for this.
PAGE 19
LTC6994-1/LTC6994-2 Applications Information Power Supply Current The Electrical Characteristics table specifies the supply current while the part is idle (waiting for an input transition). IS(IDLE) varies with the programmed tDELAY and the supply voltage, as described by the equations in Table 2, valid for both the LTC6994-1 and LTC6994-2. Table 2. Approximate Idle Supply Current Equations CONDITION TYPICAL IS(IDLE) V + • (NDIV • 7pF + 4pF ) NDIV ≤ 64 tDELAY Table 3.
PAGE 20
LTC6994-1/LTC6994-2 Applications Information Supply Bypassing and PCB Layout Guidelines The LTC6994 is an accurate monostable multivibrator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 16 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components.
PAGE 21
LTC6994-1/LTC6994-2 Typical Applications Delayed One-Shot IN OUT IN TRIG LTC6994-1 GND DELAYED PULSE OUT OUT LTC6993-1 5V V+ GND 5V V + 0.1µF SET DIV SET 604k 0.1µF 1M DIV 121k tRISE_DELAY = 50ms 392k tONESHOT = 10ms IN DELAY 50ms OUT SHOT 10ms DELAY SHOT 699412 TA02 Pulse Stretcher IN OUT OUT IN LTC6994-1 V+ GND V+ 0.
PAGE 22
LTC6994-1/LTC6994-2 Typical Applications Edge Chatter Filter IN OUT OUT IN LTC6994-2 GND V+ SET DIV 499k V+ 0.1µF 10µs INPUT MUST BE STABLE FOR AT LEAST 10µs IN OUT 10µs NORMAL 10µs 10µs NOISY EDGES 10µs 699412 TA05 Crossover Gate—Break-Before-Make Interval Timer V+ LOAD LOW IN OUT IN 100k FALLING DELAYED P TP0610 LTC6994-1 LOAD HIGH GND V+ V+ 0.
PAGE 23
LTC6994-1/LTC6994-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715 Rev A) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 (2 SIDES) 2.15 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 1.35 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 2.00 ±0.10 (2 SIDES) R = 0.05 TYP 3.00 ±0.10 (2 SIDES) 0.40 ± 0.10 4 6 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH R0.
PAGE 24
LTC6994-1/LTC6994-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.
PAGE 25
LTC6994-1/LTC6994-2 Revision History REV DATE DESCRIPTION A 7/11 Revised the Description section. PAGE NUMBER B 1/12 Added text to Basic Operation paragraph in the Applications Information section. Added MP-Grade. 1 16 1, 2, 4 Corrected sizing of the Typical Performance Characteristics curves G31 and G32. 8 699412fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 26
LTC6994-1/LTC6994-2 Typical Application Press-and-Hold (0.3s to 4s) Delay Timer V+ V+ ACTIVE HIGH OUT IN 100k 100k OUT LTC6994-1 GND SET V V+ V+ V+ GND 0.1µF 0.