LTM9011-14/ LTM9010-14/LTM9009-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs Features n n n n n n n n n n n n Description 8-Channel Simultaneous Sampling ADC 73.1dB SNR 88dB SFDR Low Power: 140mW/113mW/94mW per Channel Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Internal Bypass Capacitance, No External Components 140-Pin (11.
LTM9011-14/ LTM9010-14/LTM9009-14 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) Supply Voltages VDD, OVDD................................................. –0.3V to 2V Analog Input Voltage (AIN+, AIN –, PAR/SER, SENSE) (Note 3)........... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4)..................................... –0.3V to 3.9V SDO (Note 4).............................................. –0.3V to 3.9V Digital Output Voltage................. –0.
LTM9011-14/ LTM9010-14/LTM9009-14 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTM9011-14 PARAMETER CONDITIONS Resolution (No Missing Codes) MIN l LTM9010-14 TYP MAX MIN 14 LTM9009-14 TYP MAX MIN 14 TYP MAX UNITS 14 Bits Integral Linearity Error Differential Analog Input (Note 6) l –4.1 ±1.2 4.1 –3.25 ±1 3.25 –2.75 ±1 2.
LTM9011-14/ LTM9010-14/LTM9009-14 Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) LTM9011-14 SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 70MHz Input 140MHz Input SFDR S/(N+D) MAX LTM9010-14 MAX LTM9009-14 MIN TYP MIN TYP MIN TYP l 70.8 73.1 73 72.6 70.6 73 72.9 72.6 69.7 73 72.9 72.
LTM9011-14/ LTM9010-14/LTM9009-14 Digital Inputs And Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.
LTM9011-14/ LTM9010-14/LTM9009-14 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTM9011-14 SYMBOL PARAMETER LTM9009-14 MIN TYP MAX MIN TYP MAX MIN TYP (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.
LTM9011-14/ LTM9010-14/LTM9009-14 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTM9011-14/ LTM9010-14/LTM9009-14 Timing Diagrams 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ tDATA tSER tPD OUT#A– OUT#A+ OUT#B– OUT#B+ tSER D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD01 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+2 N tENCH ENC–
LTM9011-14/ LTM9010-14/LTM9009-14 timing DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N N+1 tENCH ENC– tENCL ENC+ tSER DCO– DCO+ FR+ tFRAME tDATA tPD tSER FR– OUT#A– OUT#A+ OUT#B– OUT#B+ tSER D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD03 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A
LTM9011-14/ LTM9010-14/LTM9009-14 timing DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D3 D2 D1 tSER D0 D13 D12 D11 D10 D9 SAMPLE N-6 D8 D7 D6 D5 D4 D3 D2 SAMPLE N-5 D1 D0 D13 D12 D11 D10 SAMPLE N-4 9009101114 TD06 OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A
LTM9011-14/ LTM9010-14/LTM9009-14 timing DIAGRAMS SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI SDO R/W HIGH IMPEDANCE A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 9009101114 TD08 9009101114fa 11
LTM9011-14/ LTM9010-14/LTM9009-14 Typical Performance Characteristics LTM9011-14: Integral Nonlinearity (INL) LTM9011-14: Differential Nonlinearity (DNL) 2.0 1.0 0 1.5 0.8 –10 0 –0.5 –1.0 0 –0.2 –0.4 0 4096 8192 12288 OUTPUT CODE –1.0 16384 0 4096 9009101114 G01 LTM9011-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 125Msps 0 –40 –50 –60 –70 –80 –90 –100 –0.
LTM9011-14/ LTM9010-14/LTM9009-14 Typical Performance Characteristics LTM9011-14: SNR vs Input Frequency, –1dBFS, 2V Range, 125Msps LTM9011-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 125Msps 95 74 110 90 90 SFDR (dBFS) 71 70 69 SFDR (dBc AND dBFS) 72 85 80 75 68 67 80 70 dBc 60 50 40 30 20 70 10 100 150 200 250 300 INPUT FREQUENCY (MHz) 65 350 0 100 150 200 250 300 INPUT FREQUENCY (MHz) 50 80 0 9009101114 G11 LTM9011-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS LTM9011-
LTM9011-14/ LTM9010-14/LTM9009-14 Typical Performance Characteristics LTM9010-14: Integral Nonlinearity (INL) LTM9010-14: Differential Nonlinearity (DNL) 2.0 1.0 0 1.5 0.8 –10 0 –0.5 –1.0 0 –0.2 –0.4 0 4096 8192 12288 OUTPUT CODE –1.0 16384 –40 –50 –60 –70 –80 –90 –100 –0.
LTM9011-14/ LTM9010-14/LTM9009-14 Typical Performance Characteristics LTM9010-14: SNR vs Input Frequency, –1dBFS, 2V Range, 105Msps LTM9010-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 105Msps 74 95 110 90 90 SFDR (dBFS) 71 70 69 SFDR (dBc AND dBFS) 72 85 80 75 68 67 80 70 dBc 60 50 40 30 20 70 10 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 65 0 50 9009101114 G24 100 150 200 250 300 INPUT FREQUENCY (MHz) LTM9010-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS 0 –80 –70
LTM9011-14/ LTM9010-14/LTM9009-14 Typical Performance Characteristics LTM9009-14: Integral Nonlinearity (INL) LTM9009-14: Differential Nonlinearity (DNL) 2.0 1.0 0 1.5 0.8 –10 0 –0.5 –1.0 0.2 0 –0.2 –0.4 –0.8 0 4096 8192 12288 OUTPUT CODE –1.0 16384 0 4096 9009101114 G29 LTM9009-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 80Msps –40 –50 –60 –70 –80 –90 –100 –0.6 –1.
LTM9011-14/ LTM9010-14/LTM9009-14 Typical Performance Characteristics LTM9009-14: SNR vs Input Frequency, –1dBFS, 2V Range, 80Msps LTM9009-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 80Msps 74 LTM9009-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps 95 73 110 100 90 70 69 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 71 85 80 75 68 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) dBc 60 50 40 30 0 –80 –70 –60 –50 –40 –30 –20
LTM9011-14/ LTM9010-14/LTM9009-14 Pin Functions AIN1+ (B2): Channel 1 Positive Differential Analog Input. AIN8+ (N1): Channel 8 Positive Differential Analog Input. AIN1– (B1): Channel 1 Negative Differential Analog Input. AIN8– (N2): Channel 8 Negative Differential Analog Input VCM12 (B3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 1 and 2. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor.
LTM9011-14/ LTM9010-14/LTM9009-14 Pin Functions OVDD (G9, G10): Output Driver Supply. OVDD is internally bypassed to ground with a 0.1µF ceramic capacitor. SDOA (E6): In serial programming mode, (PAR/SER = 0V), SDOA is the optional serial interface data output for registers controlling channels 1, 4, 5 and 8. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK.
LTM9011-14/ LTM9010-14/LTM9009-14 Pin Configuration Table 1 2 3 4 5 6 7 8 9 10 A GND GND GND GND GND GND PAR/SER O2A+ GND GND B AIN1– AIN1+ VCM12 GND GND VREF GND O2A– GND GND C – AIN2 + AIN2 GND GND SENSE GND O2B+ O1B– O4A– O4A+ D GND GND VDD VDD GND SDOB O2B– O1B+ O3A+ O3A– E AIN3– AIN3+ VDD VDD GND SDOA O1A– O1A+ O3B+ O3B– F GND GND VCM34 GND GND GND O4B– O4B+ DCOB+ DCOB– G AIN4– AIN4+ GND GND GND GND DCOA+ DCOA– OVDD
LTM9011-14/ LTM9010-14/LTM9009-14 Functional Block Diagram VDD = 1.8V OVDD = 1.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information CONVERTER OPERATION INPUT DRIVE CIRCUITS The LTM9011-14/LTM9010-14/LTM9009-14 are low power, 8-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. See back page for a DC-coupled example. 50Ω At very high frequencies an RF gain block will often have lower distortion than a differential amplifier.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information Reference The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The reference is shared by all eight ADC channels, so it is not possible to independently adjust the input range of individual channels. The LTM9011-14/LTM9010-14/LTM9009-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11).
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. serialization (see the Timing Diagrams section for details). Note that with 12-bit serialization the two LSBs are not available—this mode is included for compatibility with 12-bit versions of these parts.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode, the SCK pin can select either 3.5mA or 1.75mA.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information Digital Output Test Pattern DEVICE PROGRAMMING MODES To allow in-circuit testing of the digital interface to the A/D, there is a test mode that forces the A/D data outputs (D13-D0) of all channels to known values. The digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled, the test patterns override all other formatting modes: 2’s complement and randomizer.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information are ignored. The data transfer ends when CS is taken high again. Timing Diagrams section). During a read back command the register is not updated and data on SDI is ignored. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). The SDO pin is an open-drain output that pulls to ground with a 200Ω impedance.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information REGISTER A1 (CSB): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSB = GND) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_7 NAP_6 NAP_3 NAP_2 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 OUTTEST X TP13 TP12 TP11 TP10 TP9 TP8 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Bit 6 Unused, Don’t Care Bit.
LTM9011-14/ LTM9010-14/LTM9009-14 Applications Information Table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. These should be added to the PCB trace lengths for best matching. The material used for the substrate is BT (bismaleimidetriazine), supplied by Mitsubishi Gas and Chemical. In the DC to 125MHz range, the speed for the analog input signals is 198ps/in or 7.795ps/mm. The speed for the digital outputs is 188.5ps/in or 7.
LTM9011-14/ LTM9010-14/LTM9009-14 Typical Applications Silkscreen Top Top Side 9009101114fa 33
LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL Applications Inner Layer 2 Inner Layer 3 9009101114fa 34
LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL Applications Inner Layer 4 Inner Layer 5 9009101114fa 35
LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL Applications Bottom Side Silkscreen Bottom 9009101114fa 36
CLK+ CLK+ R27 (OPT) +1.8V GND E4 E3 C3 0.01µF R15 (OPT) C10 4.7µF 6.3V 0603 R16 (OPT) C12 1µF 0603 C19 (OPT) R37 100Ω R14 (OPT) R25 (OPT) R18 (OPT) 4 1 2 3 9 AIN1+ B2 AIN1– B1 VCM12 B3 AIN2+ C2 AIN2– C1 AIN3+ E2 AIN3– E1 VCM34 F3 AIN4+ G2 AIN4– G1 AIN5+ H2 AIN5– H1 VCM56 J3 AIN6+ K1 AIN6– K2 AIN7+ M1 AIN7– M2 AIN8+ N1 AIN8– N2 VCM78 N3 C56 0.1µF R29 180k 1% C11 1µF 0603 + CLK+ P5 CLK– P6 +1.8V D3 C5 D4 E3 4.7pF E4 K3 K4 L3 L4 +1.8VO G9 G10 R20 R24 100Ω C7 (OPT) 4.
2.000 2.000 SUGGESTED PCB LAYOUT TOP VIEW 1.200 aaa Z 0.4 Ø 140x 0.000 PACKAGE TOP VIEW 0.400 4 0.400 PIN “A1” CORNER 2.800 E 1.200 38 X D 5.200 4.400 3.600 2.800 2.000 1.200 0.400 0.400 1.200 2.000 2.800 3.600 4.400 5.200 Y 0.000 aaa Z 1.95 – 2.05 SYMBOL A A1 A2 b b1 D E e D1 E1 aaa bbb ccc ddd eee NOM 2.72 0.40 2.32 0.50 0.40 11.25 9.0 0.80 10.40 7.2 DIMENSIONS 0.15 0.10 0.12 0.15 0.08 MAX 2.87 0.45 2.42 0.55 0.
LTM9011-14/ LTM9010-14/LTM9009-14 Revision History REV DATE DESCRIPTION A 9/11 Updated Functional Block Diagram PAGE NUMBER 21 9009101114fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL Application Single-Ended to Differential Conversion Using LTC6409 and 50MHz Lowpass Filter (Only One Channel Shown). Filter for Use at 92.16Msps 0.8pF 1.8V 1.8V 0.1µF 150Ω 49.9Ω IN– + 68pF 180nH 150pF LTC6409 – SHDN 33pF 68pF OUT+ 37.4Ω VOCM 474Ω 180nH 150pF 180nH 100pF + B2 AIN1 O1A+ E8 – B1 AIN1 O1A– E7 B3 DCO+ G7 75Ω C2 0.8pF 66.9Ω 75Ω C1 F2 GND F1 50Ω VREF 180nH VDD OUT – SENSE 37.4Ω V+ IN+ B6 ••• 0.
