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Allwinner H3 Datasheet

Quad-Core OTT Box Processor

Version 1.2

Apr.23,2015

confidential

Summary of content (614 pages)

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H3 Declaration This documentation is the original work and copyrighted property of Allwinner Technology (“Allwinner”). Reproduction in whole or in part must obtain the written approval of Allwinner and give clear acknowledgement to the copyright owner. ia l The information furnished by Allwinner is believed to be accurate and reliable. Allwinner reserves the right to make changes in circuit design and/or specifications at any time without notice.
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H3 Revision History Date Description V1.0 Nov.18,2014 Initial release version V1.1 Jan.26,2015 Correct PWM Description V1.2 Apr.23,2015 Add the programming guide of crypto engine co nf id e nt ia l Version H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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H3 Table of Contents Declaration ............................................................................................................................................................................ 2 Revision History..................................................................................................................................................................... 3 Table of Contents .....................................................................................................
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H3 2.1.4.6. CCU.............................................................................................................................................. 58 2.1.4.7. PWM ........................................................................................................................................... 58 2.1.4.8. Crypto Engine(CE) ....................................................................................................................... 59 2.1.4.9. Security ID ........................
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H3 2.1.9.6. SPI................................................................................................................................................ 63 2.1.9.7. TWI .............................................................................................................................................. 63 2.1.9.8. TS ................................................................................................................................................. 63 2.1.9.9. SCR ................
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H3 4.3.5.4. PLL_VE Control Register (Default Value: 0x03006207)................................................................ 95 4.3.5.5. PLL_DDR Control Register (Default Value: 0x00001000)............................................................. 96 4.3.5.6. PLL_PERIPH0 Control Register (Default Value: 0x00041811) ...................................................... 97 4.3.5.7. PLL_GPU Control Register (Default Value: 0x03006207)............................................................. 98 4.3.
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H3 4.3.5.28. I2S/PCM 0 Clock Register (Default Value: 0x00000000) ......................................................... 115 4.3.5.29. I2S/PCM 1 Clock Register (Default Value: 0x00000000) ......................................................... 116 4.3.5.30. I2S/PCM 2 Clock Register (Default Value: 0x00000000) ......................................................... 116 4.3.5.31. OWA Clock Register (Default Value: 0x00000000) .................................................................. 116 4.3.5.
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H3 4.3.5.52. PLL_AUDIO Bias Register (Default Value: 0x10100000) .......................................................... 126 4.3.5.53. PLL_VIDEO Bias Register (Default Value: 0x10100000) ........................................................... 126 4.3.5.54. PLL_VE Bias Register (Default Value: 0x10100000) ................................................................. 126 4.3.5.55. PLL_DDR Bias Register (Default Value: 0x81104000) .............................................................. 127 4.
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H3 4.3.5.76. PS Control Register (Default Value: 0x00000000) ................................................................... 140 4.3.5.77. PS Counter Register (Default Value: 0x00000000) .................................................................. 141 4.3.6. Programming Guidelines ................................................................................................................... 142 4.3.6.1. PLL ...................................................................................
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H3 4.4.3.14. CPU System Reset Control Register(Default Value: 0x00000001) ........................................... 148 4.4.3.15. CPU Clock Gating Register(Default Value: 0x0000010F) ......................................................... 149 4.4.3.16. General Control Register(Default Value: 0x00000020) ........................................................... 149 4.4.3.17. Super Standby Flag Register(Default Value: 0x00000000) ...................................................... 149 4.4.3.18.
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H3 4.6.4.7. Timer 1 Interval Value Register ................................................................................................. 159 4.6.4.8. Timer 1 Current Value Register ................................................................................................. 160 4.6.4.9. AVS Counter Control Register (Default Value: 0x00000000) ..................................................... 160 4.6.4.10. AVS Counter 0 Register (Default Value: 0x00000000) .......................................
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H3 4.7.5.2. TWD Control Register (Default Value: 0x00000000) ................................................................. 167 4.7.5.3. TWD Restart Register (Default Value: 0x00000000) .................................................................. 168 4.7.5.4. TWD Low Counter Register (Default Value: 0x00000000) ......................................................... 168 4.7.5.5. TWD High Counter Register (Default Value: 0x00000000) ........................................................ 168 4.7.
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H3 4.8.3.9. Alarm 0 IRQ Enable Register (Default Value: 0x00000000) ....................................................... 175 4.8.3.10. Alarm 0 IRQ Status Register (Default Value: 0x00000000)...................................................... 176 4.8.3.11. Alarm 1 Week HH-MM-SS Register (Default Value: 0x00000000) .......................................... 176 4.8.3.12. Alarm 1 Enable Register (Default Value: 0x00000000) ........................................................... 176 4.8.3.13.
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H3 4.9.4.5. HS Timer Interval Value Hi Register .......................................................................................... 185 4.9.4.6. HS Timer Current Value Lo Register .......................................................................................... 186 4.9.4.7. HS Timer Current Value Hi Register .......................................................................................... 186 4.9.5. 4.10. Programming Guidelines ......................................................
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H3 4.11.4.6. DMA Auto Gating Register (Default Value: 0x00000000)........................................................ 201 4.11.4.7. DMA Status Register (Default Value: 0x00000000) ................................................................. 201 4.11.4.8. DMA Channel Enable Register (Default Value: 0x00000000) .................................................. 202 4.11.4.9. DMA Channel Pause Register (Default Value: 0x00000000) ................................................... 203 4.11.4.10.
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H3 4.13.5.1. MSGBox Control Register 0(Default Value: 0x10101010) ....................................................... 214 4.13.5.2. MSGBox Control Register 1(Default Value: 0x10101010) ....................................................... 215 4.13.5.3. MSGBox IRQ Enable Register (Default Value: 0x00000000) .................................................... 216 4.13.5.4. MSGBox IRQ Status Register u(Default Value: 0x0000AAAA).................................................. 217 4.13.5.5.
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H3 4.15.2.1. Block Diagram ......................................................................................................................... 227 4.15.2.2. Crypto Engine Task Descriptor................................................................................................. 227 4.15.3. Crypto Engine Register List ................................................................................................................ 230 4.15.4. Crypto Engine Register Description ...................
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H3 4.17.2.3. Region Size Table ..................................................................................................................... 239 4.17.2.4. Security inversion is disabled .................................................................................................. 239 4.17.2.5. Security inversion is enabled................................................................................................... 240 4.17.3. SMC Register List .............................................
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H3 4.17.4.20. SMC Region Setup High Register(Default Value: 0x00000000)............................................. 247 4.17.4.21. SMC Region Attributes Register(Default Value: 0x00000000) .............................................. 248 4.18. Secure Memory Touch Arbiter .................................................................................................................. 249 4.18.1. Overview ................................................................................................
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H3 4.19.4.2. THS Control Register1 (Default Value: 0x00000000) ............................................................... 255 4.19.4.3. ADC calibration Data Register (Default Value: 0x00000000) .................................................. 256 4.19.4.4. THS Control Register2 (Default Value: 0x00040000) ............................................................... 256 4.19.4.5. THS Interrupt Control Register (Default Value: 0x00000000).................................................. 256 4.19.4.
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H3 4.21.2.2. Filter/Reference ...................................................................................................................... 266 4.21.2.3. Power/Ground......................................................................................................................... 266 4.21.3. Data Path Diagram ............................................................................................................................ 266 4.21.4. Audio Codec Register List ...................
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H3 4.21.5.20. 0x8C ADC DAP Right Decay & Attack Time Register(Default Value: 0x0000001F) ................ 283 4.21.5.21. 0x90 ADC DAP HPF Coef Register(Default Value: 0x00FF_FAC1) .......................................... 284 4.21.5.22. 0x94 ADC DAP Left Input Signal Low Average Coef Register(Default Value: 0x00051EB8) ... 284 4.21.5.23. 0x98 ADC DAP Right Input Signal Low Average Coef Register(Default Value: 0x00051EB8) . 284 4.21.5.24. 0x9C ADC DAP Optimum Register(Default Value: 0x00000000) ............
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H3 289 4.21.5.41. 0x140 DAC DRC Compressor Threshold High Setting Register(Default Value: 0x0000_D3C0) 289 4.21.5.42. 0x144 DAC DRC Compressor Slope High Setting Register(Default Value: 0x00000080) ...... 290 4.21.5.43. 0x148 DAC DRC Compressor Slope Low Setting Register(Default Value: 0x0000_0000) ..... 290 4.21.5.44. 0x14C DAC DRC Compressor High Output at Compressor Threshold Register( Default Value: 0x0000F95B) .............................................................................................
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H3 4.21.5.61. 0x190 DAC DRC Smooth filter Gain Low Attack Time Coef Register(Default Value: 0x00005600) ............................................................................................................................................. 293 4.21.5.62. 0x194 DAC DRC Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000) ............................................................................................................................................. 294 4.21.5.63.
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H3 4.21.5.81. 0x224 ADC DRC Right Peak filter High Release Time Coef Register(Default Value: 0x000000FF) 298 4.21.5.82. 0x228 ADC DRC Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8) 299 4.21.5.83. 0x22C ADC DRC Left RMS Filter High Coef Register(Default Value: 0x00000001) ................ 299 4.21.5.84. 0x230 ADC DRC Left RMS Filter Low Coef Register(Default Value: 0x00002BAF) ................ 299 4.21.5.85.
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H3 4.21.5.103. 0x27C ADC DRC Expander High Output at Expander Threshold(Default Value: 0x0000F45F) 303 4.21.5.104. 0x280 ADC DRC Expander Low Output at Expander Threshold(Default Value: 0x00008D6E) 303 4.21.5.105. 0x284 ADC DRC Linear Slope High Setting Register(Default Value: 0x00000100) .............. 303 4.21.5.106. 0x288 ADC DRC Linear Slope Low Setting Register(Default Value: 0x00000000)............... 303 4.21.5.107.
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H3 4.21.6.5. 0x03 DAC Analog Enable and PA Source Control Register(Default Value: 0x00) ..................... 308 4.21.6.6. 0x05 Linein and Gain Control Register(Default Value: 0x30) .................................................. 308 4.21.6.7. 0x06 MIC1 And MIC2 Gain Control Register(Default Value: 0x33) .......................................... 309 4.21.6.8. 0x07 PA Enable and LINEOUT Control Register(Default Value: 0x04) ..................................... 309 4.21.6.9.
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H3 4.22.2.2. PA Configure Register 1 (Default Value: 0x77777777) ............................................................ 318 4.22.2.3. PA Configure Register 2 (Default Value: 0x00777777) ............................................................ 319 4.22.2.4. PA Configure Register 3 (Default Value: 0x00000000) ............................................................ 320 4.22.2.5. PA Data Register (Default Value: 0x00000000) .......................................................................
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H3 4.22.2.26. PD PULL Register 0 (Default Value: 0x00000000).................................................................. 330 4.22.2.27. PD PULL Register 1 (Default Value: 0x00000000).................................................................. 330 4.22.2.28. PE Configure Register 0 (Default Value: 0x77777777) .......................................................... 330 4.22.2.29. PE Configure Register 1 (Default Value: 0x77777777) ..........................................................
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H3 4.22.2.50. PG Data Register (Default Value: 0x00000000) ..................................................................... 339 4.22.2.51. PG Multi-Driving Register 0 (Default Value: 0x05555555) .................................................... 339 4.22.2.52. PG Multi-Driving Register 1 (Default Value: 0x00000000) .................................................... 340 4.22.2.53. PG PULL Register 0 (Default Value: 0x00000000) ................................................................. 340 4.
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H3 4.23.2.3. PL Configure Register 2 (Default Value: 0x00000000)............................................................. 347 4.23.2.4. PL Configure Register 3 (Default Value: 0x00000000)............................................................. 347 4.23.2.5. PL Data Register (Default Value: 0x00000000) ........................................................................ 348 4.23.2.6. PL Multi-Driving Register 0 (Default Value: 0x00555555) .......................................................
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H3 5.2.6.1. NDFC Control Register(Default Value: 0x00000000)................................................................. 362 5.2.6.2. NDFC Status Register(Default Value: 0x00000000)................................................................... 364 5.2.6.3. NDFC Interrupt and DMA Enable Register(Default Value: 0x00000000) .................................. 365 5.2.6.4. NDFC Timing Control Register(Default Value: 0x00000000)..................................................... 366 5.2.6.5.
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H3 5.2.6.25. NDFC Read Data Status Control Register(Default Value: 0x01000000) .................................. 376 5.2.6.26. NDFC Read Data Status Register 0(Default Value: 0x00000000) ............................................ 376 5.2.6.27. NDFC Read Data Status Register 1(Default Value: 0x00000000) ............................................ 376 5.2.6.28. NDFC MBUS DMA Address Register(Default Value: 0x00000000) .......................................... 377 5.2.6.29.
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H3 5.3.7.6. SD Block Count Register (Default Value: 0x00000200) ............................................................. 386 5.3.7.7. SD Command Register (Default Value: 0x00000000)................................................................ 386 5.3.7.8. SD Command Argument Register (Default Value: 0x00000000)............................................... 388 5.3.7.9. SD Response 0 Register (Default Value: 0x00000000) .............................................................. 388 5.3.7.10.
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H3 5.3.7.30. SD Data6 CRC Register (Default Value: 0x00000000).............................................................. 400 5.3.7.31. SD Data5 CRC Register (Default Value: 0x00000000).............................................................. 400 5.3.7.32. SD Data4 CRC Register (Default Value: 0x00000000).............................................................. 400 5.3.7.33. SD Data3 CRC Register (Default Value: 0x00000000).............................................................. 401 5.3.
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H3 6.1.4.6. CSI Pattern Generation Length Register (Default Value: 0x00000000) ..................................... 411 6.1.4.7. CSI Pattern Generation Address Register (Default Value: 0x00000000) ................................... 411 6.1.4.8. CSI Version Register (Default Value: 0x00000000) ................................................................... 411 6.1.4.9. CSI Channel_0 configuration Register (Default Value: 0x00300200) ........................................ 411 6.1.4.10.
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H3 6.1.4.30. CCI Line Counter Trigger Control Register (Default Value: 0x00000000) ................................ 422 6.1.4.31. CCI FIFO Acess Register (Default Value: 0x00000000) ............................................................ 422 7.1. Display ....................................................................................................................................................... 423 DE2.0 ........................................................................................
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H3 7.2.5.12. TCON CEU Coefficient Mul Register (Default Value: 0x00000000) ......................................... 430 7.2.5.13. TCON CEU Coefficient Add Register (Default Value: 0x00000000) ......................................... 431 7.2.5.14. TCON CEU Coefficient Range Register (Default Value: 0x00000000)...................................... 431 7.2.5.15. TCON1 Fill Control Register (Default Value: 0x00000000) ...................................................... 432 7.2.5.16.
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H3 7.2.7.16. TCON1 Fill Begin Register (Default Value: 0x00000000) ......................................................... 438 7.2.7.17. TCON1 Fill End Register (Default Value: 0x00000000)............................................................ 438 7.2.7.18. TCON1 Fill Data Register (Default Value: 0x00000000) .......................................................... 439 Chapter 8 8.1. Interfaces.........................................................................................................
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H3 8.2.2. SPI Timing Diagram ........................................................................................................................... 450 8.2.3. SPI Pin List ......................................................................................................................................... 451 8.2.4. SPI Register List ................................................................................................................................. 451 8.2.5.
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H3 8.3.5.2. UART Transmit Holding Register(Default Value: 0x00000000) ................................................. 467 8.3.5.3. UART Divisor Latch Low Register(Default Value: 0x00000000)................................................. 467 8.3.5.4. UART Divisor Latch High Register(Default Value: 0x00000000) ................................................ 468 8.3.5.5. UART Interrupt Enable Register(Default Value: 0x00000000) .................................................. 468 8.3.5.6.
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H3 8.4.3.6. CIR Receiver Configure Register(Default Value: 0x00000000) .................................................. 484 8.5. USB ............................................................................................................................................................ 486 8.5.1. USB OTG Controller ........................................................................................................................... 486 8.5.1.1. Overview .........................................
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H3 8.6.5.1. System setup and I2S/PCM initialization................................................................................... 527 8.6.5.2. The channel setup and DMA setup ........................................................................................... 527 8.6.5.3. Enable and disable the I2S/PCM ............................................................................................... 527 8.6.6. I2S/PCM Register List ..................................................................
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H3 8.7.2. Functional Description ...................................................................................................................... 542 8.7.2.1. OWA Interface Pin List............................................................................................................... 542 8.7.2.2. OWA Clock Requirement ........................................................................................................... 542 8.7.2.3. OWA Block Diagram .....................................
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H3 8.8.1. Overview ........................................................................................................................................... 558 8.8.2. Block Diagram ................................................................................................................................... 558 8.8.3. SCR Timing Diagram .......................................................................................................................... 559 8.8.4. SCR Special Requirement .
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H3 8.9.4.1. Basic Control 0 Register(Default Value: 0x00000000) .............................................................. 572 8.9.4.2. Basic Control 1 Register(Default Value: 0x08000000) .............................................................. 572 8.9.4.3. Interrupt Status Register(Default Value: 0x00000000) ............................................................. 573 8.9.4.4. Interrupt Enable Register(Default Value: 0x00000000) ............................................................
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H3 8.9.4.25. Receive DMA Current Descriptor Register(Default Value: 0x00000000) ................................ 584 8.9.4.26. Receive DMA Current Buffer Address Register(Default Value: 0x00000000) ......................... 584 8.9.4.27. 8.9.5. RGMII Status Register(Default Value: 0x00000000)................................................................ 584 EMAC RX/TX Descriptor..................................................................................................................... 584 8.9.
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H3 8.10.4.14. TSF Control and Status Register(Default Value: 0x00000000) ............................................... 598 8.10.4.15. TSF Packet Parameter Register(Default Value: 0x00470000) ................................................ 598 8.10.4.16. TSF Interrupt Enable and Status Register(Default Value: 0x00000000) ................................ 599 8.10.4.17. TSF DMA Interrupt Enable Register(Default Value: 0x00000000) ......................................... 600 8.10.4.18.
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H3 8.10.4.38. TSD Control Word Register(Default Value: 0x00000000) ...................................................... 605 Chapter 9 Electrical Characteristics ........................................................................................................................... 607 9.1. Absolute Maximum Ratings ...................................................................................................................... 607 9.2. Recommended Operating Conditions .........................
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About This Documentation Chapter 1 About This Documentation 1.1. Documentation Overview This documentation provides an overall description of the Allwinner quad-core H3 application processor, which will provide instructions to programmers from several sections, including system, memory, image, display and interface. 1.2. Acronyms and abbreviations The table below contains acronyms and abbreviations used in this document.
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About This Documentation CSI CMOS Sensor Interface The hardware block that interfaces with different image sensor interfaces and provides a standard output that can be used for subsequent image processing Data Encryption Standard A previously predominant algorithm for the encryption of electronic data Delay-Locked Loop A digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal voltage-controlled oscillator, replaced by a delay line Dynamic Range
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About This Documentation HDMI High-Definition Multimedia Interface A compact audio/video interface for transmitting uncompressed digital data Inter IC Sound An electrical serial bus interface standard used for connecting digital audio devices together Least Significant Bit The bit position in a binary integer giving the units value, that is, determining whether the number is even or odd.
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About This Documentation National Television System Committee An analog television system that is used in most of North America, and many other countries Open Host Controller Interface A register-level interface that enables a host controller for USB to communicate with a host controller driver in software PAL Phase Alternating Line An analogue television color encoding system used in broadcast television systems in many countries PCM Pulse Code Modulation A method used to digitally represent samp
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Overview Chapter 2 Overview The Allwinner H3 is a highly cost-efficient quad-core OTT Box processor, which is a part of growing home entertainment products that offers high-performance processing with a high degree of functional integration. The H3 processor has some very exciting features, for example: co nf id e nt ia l • CPU architecture: Quad-core CortexTM-A7 with separately NEON coprocessor, the most power efficient CPU core ARM’s ever developed.
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Overview 2.1. Processor Features 2.1.1. CPU Architecture 2.1.3. Memory Subsystem     • co 2.1.3.1. Boot ROM id e ARM Mali400MP2 GPU Support OpenGL ES 2.0 and OpenVG 1.1 standard nf   GPU Architecture nt 2.1.2.
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Overview      16 address signal lines and 3 bank signal lines 32-bits bus width Support clock frequency up to 667 MHz(DDR3-1333) Runtime-configurable parameters setting for application flexibility Random read or write operation is supported Up to 2 flash chips 8-bit data bus width Up to 64-bit ECC per 1024 bytes Support 1024, 2048, 4096, 8192, 16K bytes size per page Support SLC/MLC/TLC flash and EF-NAND memory Support SDR, ONFI DDR and Toggle DDR NAND Embedded DMA to do data transfer Support data tr
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Overview 2.1.4.2. High Speed Timer   Counters up to 56 bits Clock source is synchronized with AHB clock, much more accurate than other timers 2.1.4.3. RTC     Time,calendar Counters second,minutes,hours,day,week,month and year with leap year generator Alarm:general alarm and weekly alarm One 32KHz fanout ia l 2.1.4.4. GIC id e nt  Support 16 Software Generated Interrupts(SGIs), 16 Private Peripheral Interrupts(PPIs) and 125 Shared Peripheral Interrupts(SPIs) 2.1.4.5.
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Overview 2.1.4.8.
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Overview   Support SmartColor 2.0 for excellent display experience - Adaptive edge sharping - Adaptive color enhancement - Adaptive contrast enhancement and fresh tone rectify Support writeback for high efficient dual display 2.1.6. Video Engine 2.1.6.1. Video Decoding Support multi-format video playback, including: - H.265:1080p@60fps,4K@30fps - H.
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Overview 2.1.7. Image Subsystem 2.1.7.1. CSI     Support 8-bits YUV422 CMOS sensor interface Support CCIR656 protocol for NTSC and PAL Support up to 5M pixel camera sensor Support video capture resolution up to 1080p@30fps 2.1.8.
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Overview     Full-duplex synchronous work mode Mater and slave mode configured Adjustable audio sample resolution from 8-bit to 32-bit Sample rate from 8KHz to 192KHz 2.1.9. External Peripherals 2.1.9.1. USB ia l nt  One USB 2.0 OTG,with integrated USB PHY Complies with USB2.0 Specification Support High-Speed (HS,480Mbps),Full-Speed(FS,12Mbps) and Low-Speed(LS,1.5Mbps) in host mode Complies with Enhanced Host Controller Interface(EHCI)Specification, Version 1.
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Overview 2.1.9.4. CIR   A flexible receiver for IR remote Programmable FIFO threshold 2.1.9.5. UART     Up to five UART controllers 64-Bytes Transmit and receive data FIFOs for all UART Compatible with industry-standard 16550 UARTs Support Infrared Data Association(IrDA) 1.
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Overview 2.1.9.9. SCR Supports APB slave interface for easy integration with AMBA-based host systems Supports the ISO/IEC 7816-3:1997(E) and EMV2000 (4.
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Overview 2.2. System Block Diagram co nf id e nt ia l Figure 2-1 shows the block diagram of H3 processor. H3 Datasheet(Revision1.2) Figure 2-1. H3 Block Diagram Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Pin Description Chapter 3 Pin Description 3.1. Pin Characteristics Table 3-1 lists the characteristics of H3 Pins from seven aspects: BALL#, Pin Name, Default Function, Type, Reset State, Default Pull Up/Down, and Buffer Strength. Table 3-1.
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Default Buffer Strength Pull Up/Down (mA) Z - - I/O Z - - DRAM I/O Z - - SDQ6 DRAM I/O Z - - U20 SDQ7 DRAM I/O Z - - J19 SDQ8 DRAM I/O Z - - H20 SDQ9 DRAM I/O Z - - H21 SDQ10 DRAM I/O Z - - J21 SDQ11 DRAM I/O Z - - L20 SDQ12 DRAM I/O Z - - L21 SDQ13 DRAM I/O Z - - M21 SDQ14 DRAM I/O Z - - M19 SDQ15 DRAM I/O Z - - Y17 SDQ16 DRAM I/O Z - - AA17 SDQ17 DRAM I/O ia l Pin Description Z - - Y16 SDQ18 DRAM W15 S
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Pin Description Default Buffer Strength Pull Up/Down (mA) Z - - O Z - - DRAM O Z - - SRST DRAM O Z - - T16 SVREF DRAM P Z - - W13 SWE DRAM O Z - - V10 SZQ DRAM A Z - - VCC-DRAM POWER P - - - D11 PA0 GPIO I/O Z NO PULL 20 D5 PA1 GPIO I/O Z NO PULL 20 D6 PA2 GPIO I/O Z NO PULL 20 E13 PA3 GPIO I/O Z NO PULL 20 F5 PA4 GPIO I/O Z NO PULL 20 H6 PA5 GPIO I/O Z NO PULL 20 E14 PA6 GPIO I/O Z NO PULL 20 D8 PA7 F13 PA
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Pin Description Default Buffer Strength Pull Up/Down (mA) Z NO PULL 20 I/O Z Pull-Up 20 GPIO I/O Z Pull-Up 20 PC8 GPIO I/O Z NO PULL 20 C17 PC9 GPIO I/O Z NO PULL 20 D17 PC10 GPIO I/O Z NO PULL 20 C18 PC11 GPIO I/O Z NO PULL 20 B17 PC12 GPIO I/O Z NO PULL 20 B19 PC13 GPIO I/O Z NO PULL 20 F17 PC14 GPIO I/O Z NO PULL 20 C19 PC15 GPIO I/O Z NO PULL 20 H16 PC16 GPIO I/O Z NO PULL 20 C21 PD0 GPIO I/O H17 PD1 GPIO I/O B20 PD2
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Pin Description Default Buffer Strength Pull Up/Down (mA) Z NO PULL 20 I/O Z NO PULL 20 GPIO I/O Z NO PULL 20 PE11 GPIO I/O Z NO PULL 20 B12 PE12 GPIO I/O Z NO PULL 20 C7 PE13 GPIO I/O Z NO PULL 20 C6 PE14 GPIO I/O Z NO PULL 20 C5 PE15 GPIO I/O Z NO PULL 20 D19 PF0 GPIO I/O Z NO PULL 20 A19 PF1 GPIO I/O Z NO PULL 20 D20 PF2 GPIO I/O Z NO PULL 20 F18 PF3 GPIO I/O Z NO PULL 20 E21 PF4 GPIO I/O Z NO PULL 20 C20 PF5 GPIO I/
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Pin Description Default Buffer Strength Pull Up/Down (mA) Z NO PULL 20 I/O Z NO PULL 20 GPIO I/O Z NO PULL 20 PL11 GPIO I/O Z NO PULL 20 W6 UBOOT - I - Pull-Up - T5 TEST - I - Pull-Down - AA6 NMI - I - NO PULL - V6 RESET - I - NO PULL - L5 PLLTEST - A - - - P3 X32KFOUT - A - - - K2 X24MIN - A - - - K1 X24MOUT - A - - - K6 VCC_RTC - P - - - N3 VCC_PLL - P - - - G5 HCEC - M2 HHPD - H3 HSCL K3 HSDA F1 HTX0N
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Pin Description Default Buffer Strength Pull Up/Down (mA) - - - P - - - - A - - - LINEINR - A - - - AA3 LINEOUTL - A - - - Y3 LINEOUTR - A - - - W3 MBIAS - A - - - Y1 MICIN1N - A - - - W2 MICIN1P - A - - - AA2 MICIN2N - A - - - Y2 MICIN2P - A - - - Y4 VRA1 - A - - - W5 VRA2 - A - - - V4 VRP - A - - - A2 EPHY_LINK_LED - F6 EPHY_RTX - A4 EPHY_RXN - B4 EPHY_RXP F7 EPHY_SPD_LED A3 EPHY_TXN B3 EPHY_TXP G
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Default Buffer Strength Pull Up/Down (mA) - - - P - - - - P - - - VDD_CPUS - P - - - VDD-SYS - P - - - GND - G ia l Pin Description Default - - - - Ball# Pin Name Type Reset State H11 VDD_EFUSEEBP - P G10 VDD_EFUSE - VDD_CPUX Function N8,P6,P7,P8,P9,R6, R7, R8,T6,T7, T8,U6,U9 J7,J8 H10,J10,J11,J12,K1 0,K11,K12,L10,L11, L12,L13, L14 A21,AA1,G8,H12, H15, J13,J16, J9, K13, K14,K15, K16, K7,K8,K9,L15,L8,L9, M13,M14,M15,M7, M8,M9,N10,N11, N12,N13,N14,N15, R11,R
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Pin Description 3.2. GPIO Multiplexing Functions Table 3-2 provides a description of the H3 GPIO multiplexing functions. Table 3-2.
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Pin Description Pin Default IO Default Name Function Type IO State PC12 I/O DIS PC13 I/O PC14 Default Pull-up/ Function 2 Function3 Function 4 Function 5 Function 6 Z NAND_DQ4 SDC2_D4 - - - DIS Z NAND_DQ5 SDC2_D5 - - - I/O DIS Z NAND_DQ6 SDC2_D6 - - - PC15 I/O DIS Z NAND_DQ7 SDC2_D7 - - - PC16 I/O DIS Z NAND_DQS SDC2_RST - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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Pin Description Pin Default IO Default Name Function Type IO State Default Pull-up/ Function 2 Function3 Function 4 Function 5 Function 6 - - - - - - - - - - - - down MII_TXCK/RMI I_TXCK RGMII_TXCTL/ PD13 I/O DIS Z MII_TXEN/RMI I_TXEN RGMII_NULL/ PD14 I/O DIS Z MII_TXERR/R MII_NULL RGMII_CLKIN/ PD15 I/O DIS Z MII_COL/RMII _NULL I/O DIS Z MDC - - - - PD17 I/O DIS Z MDIO - - - - PE0 I/O DIS Z CSI_PCLK TS_CLK - - - PE1 I/O DIS Z CSI_MCLK
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Pin Description Pin Default IO Default Name Function Type IO State PG5 I/O DIS PG6 I/O PG7 Default Function 2 Function3 Function 4 Function 5 Function 6 Z SDC1_D3 - - - PG_EINT5 DIS Z UART1_TX - - - PG_EINT6 I/O DIS Z UART1_RX - - - PG_EINT7 PG8 I/O DIS Z UART1_RTS - - - PG_EINT8 PG9 I/O DIS Z UART1_CTS - - - PG_EINT9 PG10 I/O DIS Z PCM1_SYNC - - - PG_EINT10 PG11 I/O DIS Z PCM1_CLK - - - PG_EINT11 PG12 I/O DIS Z PCM1_DOUT - -
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Pin Description 3.3. Detailed Pin/Signal Description Table 3-3 shows the detailed function description of every pin/signal based on the different interface. Table 3-3.
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Pin Description Pin/Signal Name Description Type HTX1N HDMI negative TMDS differential line driver data1 output AO HTX2P HDMI positive TMDS differential line driver data2 output AO HTX2N HDMI negative TMDS differential line driver data2 output AO HTXCP HDMI positive TMDS differential line driver clock output AO HTXCN HDMI negative TMDS differential line driver clock output AO HVCC HDMI Power Supply P HHPD HDMI Hot Plug Detection signal I/O HCEC HDMI Consumer Electronics Control I/O
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Description Type EPHY_RXP Transceiver Positive Output/Input A I/O EPHY_RXN Transceiver Negative Output/Input A I/O EPHY_TXP Transceiver Positive Output/Input A I/O EPHY_TXN Transceiver Negative Output/Input A I/O EPHY_RTX EPHY External Resistance to Ground AI EPHY_LINK_LED EPHY LINK Up/Down Indicator LED O EPHY_SPD_LED EPHY 10M/100M Indicator LED O EPHY_VDD Analog Power Supply for EPHY P EPHY_VCC Analog Power Supply for EPHY P SDC0_CMD Command Signal for SD/TF Card I/O SDC0_C
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Pin Description Pin/Signal Name Description Type CSI_HSYNC CSI Horizontal SYNC I CSI_VSYNC CSI Vertical SYNC I CSI_D[7:0] CSI Data bit [7:0] I CSI_SCK CSI Command Serial Clock Signal I/O CSI_SDA CSI Command Serial Data Signal I/O RGMII/MII Receive Data I RGMII/MII Receive Data I RGMII/MII /RMII Receive Data I RGMII/MII /RMII Receive Data I RGMII_RXD3/MII_RXD3 /RMII_NULL RGMII_RXD2/MII_RXD2/ RMII_NULL RGMII_RXD1/MII_RXD1/ RMII_RXD1 RGMII_RXD0/MII_RXD0/ RMII_RXD0 RGMII_RXCK/MII_RXCK/
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Pin/Signal Name Description Type TS_SYNC Transport Stream Sync I TS_DVLD Transport Stream Valid Signal I TS_D[7:0] Transport Stream Data I SPIx_CS SPIx Chip Select signal, low active I/O SPIx_CLK SPIx Clock signal I/O SPIx_MOSI SPIx Master data Out, Slave data In I/O SPIx_MISO SPIx Master data In, Slave data Out I/O UART0_TX UART0 Data Transmit O UART0_RX UART0 Data Receive I UART1_TX UART1 Data Transmit O UART1_RX UART1 Data Receive I UART1_CTS UART1 Data Clear To Send
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System Chapter 4 System nt id e nf Memory Mapping Boot System CCU CPU Configuration System Control Timer Trusted Watchdog RTC High-speed Timer PWM DMA GIC Message Box Spinlock Crypto Engine Security ID Secure Memory Controller Secure Memory Touch Arbiter Thermal Sensor Controller KEY_ADC Audio Codec Port Controller(CPU-PORT) Port Controller(CPUs-PORT) co                        ia l The chapter describes the H3 system from following sections: H3 Datasheet(Revision1.
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System 4.1.
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System 0x01C2 8400---0x01C2 87FF 1K UART 2 0x01C2 8800---0x01C2 8BFF 1K UART 3 0x01C2 8C00---0x01C2 8FFF 1K TWI 0 0x01C2 AC00---0x01C2 AFFF 1K TWI 1 0x01C2 B000---0x01C2 B3FF 1K TWI 2 0x01C2 B400---0x01C2 B7FF 1K SCR 0x01C2 C400---0x01C2 C7FF 1K EMAC 0x01C3 0000---0x01C3 FFFF 64K GPU 0x01C4 0000---0x01C4 FFFF 64K HSTMR 0x01C6 0000---0x01C6 0FFF 4K DRAMCOM 0x01C6 2000---0x01C6 2FFF 4K DRAMCTL0 0x01C6 3000---0x01C6 3FFF 4K DRAMPHY0 0x01C6 5000---0x01C6 5FFF 4K SPI0 0x01C
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System 4.2. Boot System The Boot System includes the following features: ia l nt • id e • nf • The system will boot in different ways based on whether its security features are enabled Support CPU-0 boot process and CPU-0+ boot process Support super standby wakeup process Support mandatory upgrade process through SDC0 and USB OTG Support fast boot process from Raw NAND,eMMC,SD/TF card ,and SPI NOR Flash co • • H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.
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System 4.3. CCU 4.3.1. Overview nt Functionalities Description co 4.3.2.1. System Bus nf 4.3.2. id e The CCU includes the following features:  9 PLLs, independent PLL for CPUX  Bus Source and Divisions  PLLs Bias Control  PLLs Tunning Control  PLLs Pattern Control  Configuring Modules Clock  Bus Clock Gating  Bus Software Reset ia l The CCU controls the PLLs configuration and most of the clock generation, division, distribution, synchronization and gating.
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System 4.3.2.2. Bus clock tree System ATB / APB ATB_ APB_CLK_DIV ( 1/ 2/ 4) INOSC / 512 MUX CPUX PLL_CPUX /1 L 2 Cache AXI_ CLK_ DIV_ RATIO (1~4) ia l AXI 24M Hz MUX AHB1 nt X AHB_CLK_ RATIO (1/2/3/4) id e AHB_ PRE_ DIV (1~4) MUX CLK_PRE_DIV (1/2/4/8) APB1 CLK_ RATIO (1~32) APB2 co nf PERIPH_ PLL APB_ CLK_ RATIO (1/2/4/8) Figure 4-2. Bus Clock Tree 4.3.3.
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System   Clock output of PLL_HSIC can be used for CCI-400 and USBPHY, and dynamic frequency scaling is not supported; Clock output of PLL_GPU can be used for GPU, and dynamic frequency scaling is not supported; 4.3.4.
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0x0118 TCON0 Clock Register TVE_CLK_REG 0x0120 TVE Clock Register DEINTERLACE_CLK_REG 0x0124 DEINTERLACE Clock Register CSI_MISC_CLK_REG 0x0130 CSI_MISC Clock Register CSI_CLK_REG 0x0134 CSI Clock Register VE_CLK_REG 0x013C VE Clock Register AC_DIG_CLK_REG 0x0140 AC Digital Clock Register AVS_CLK_REG 0x0144 AVS Clock Register HDMI_CLK_REG 0x0150 HDMI Clock Register HDMI_SLOW_CLK_REG 0x0154 HDMI Slow Clock Register MBUS_CLK_REG 0x015C MBUS Clock Register GPU_CLK_REG 0x01A0 G
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System 4.3.5. Register Description 4.3.5.1. PLL_CPUX Control Register (Default Value: 0x00001000) Offset: 0x0000 Register Name: PLL_CPUX_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE. 0: Disable 1: Enable The PLL Output= (24MHz*N*K)/(M*P). The PLL output is for the CPUX Clock. Note: The PLL output clock must be in the range of 200MHz~2.6GHz. Its default is 408MHz. 30:29 / / / 28 R 0x0 LOCK 0: Unlocked 1: Locked (It indicates that the PLL has been stable.
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System PLL Factor M. (M=Factor + 1) The range is from 1 to 4. 4.3.5.2. PLL_Audio Control Register (Default Value: 0x00035514) Offset: 0x0008 Register Name: PLL_AUDIO_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE. 0: Disable 1: Enable. The PLL is for Audio. PLL _AUDIO = (24MHz*N)/(M*P) PLL_AUDIO(8X)= (24MHz*N*2)/M PLL_AUDIO(4X)=PLL_AUDIO(8X)/2 PLL_AUDIO(2X)=PLL_AUDIO(4X)/2 The PLL output clock must be in the range of 20MHz~200MHz. Its default is 24.571MHz.
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System 4.3.5.3. PLL_VIDEO Control Register (Default Value: 0x03006207) Offset: 0x0010 Register Name: PLL_VIDEO_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE. 0: Disable 1: Enable In the integer mode,the PLL Output = (24MHz*N)/M. In the fractional mode, the PLL Output is select by bit 25. Note: In the Clock Control Module, PLL(1X) Output=PLL while PLL(2X) Output=PLL * 2. The PLL output clock must be in the range of 30MHz~600MHz. Its default is 297MHz. 30 R/W 0x0 PLL_MODE.
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System The range is from 1 to 16. 4.3.5.4. PLL_VE Control Register (Default Value: 0x03006207) Offset: 0x0018 Register Name: PLL_VE_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE. 0: Disable 1: Enable In the integer mode, The PLL Output = (24MHz*N)/M. In the fractional mode, the PLL Output is select by bit 25. Note: The PLL output clock must be in the range of 30MHz~600MHz. Its default is 297MHz.
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System The range is from 1 to 16. 4.3.5.5. PLL_DDR Control Register (Default Value: 0x00001000) Offset: 0x0020 Register Name: PLL_DDR_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE. 0: Disable 1: Enable Set bit20 to validate the PLL after this bit is set to 1. The PLL Output = (24MHz*N*K)/M. Note: the PLL output clock must be in the range of 200MHz~2.6GHz. Its default is 408MHz. 30:29 / / / 28 R 0x0 LOCK 0: Unlocked 1: Locked (It indicates that the PLL has been stable.
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System The range is from 1 to 4. 4.3.5.6. PLL_PERIPH0 Control Register (Default Value: 0x00041811) Offset: 0x0028 Register Name: PLL_PERIPH0_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE. 0: Disable 1: Enable The PLL Output = 24MHz*N*K/2. Note: The PLL Output should be fixed to 600MHz, it is not recommended to vary this value arbitrarily. In the Clock Control Module, PLL(2X) output= PLL*2 = 24MHz*N*K. The PLL output clock must be in the range of 200MHz~1.8GHz. Its default is 600MHz.
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System …… Factor=31, N=32 7:6 / / / 5:4 R/W 0x1 PLL_FACTOR_K. PLL Factor K.(K=Factor + 1 ) The range is from 1 to 4. 3:2 / / / 1:0 R/W 0x1 PLL_FACTOR_M. PLL Factor M (M = Factor + 1) is only valid in plltest debug. The PLL_PERIPH back door clock output =24MHz*N*K/M. The range is from 1 to 4. Offset: 0x0038 ia l 4.3.5.7. PLL_GPU Control Register (Default Value: 0x03006207) Register Name: PLL_GPU_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE.
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System Factor=0, N=1 Factor=1, N=2 Factor=2, N=3 …… Factor=127, N=128 7:4 / / / 3:0 R/W 0x7 PLL_PRE_DIV_M. PLL Pre Divider (M = Factor+1). The range is from 1 to 16. 4.3.5.8. PLL_PERIPH1 Control Register (Default Value: 0x00041811) Offset: 0x0044 Register Name: PLL_PERIPH1_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 PLL_ENABLE. 0: Disable 1: Enable The PLL Output = 24MHz*N*K/2. Note: The PLL Output should be fixed to 600MHz, it is not recommended to vary this value arbitrarily.
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System 0: Disable 1: Enable When 25MHz crystal used, this PLL can output 24MHz. R/W 0x0 PLL_24M_POST_DIV. PLL 24M Output Clock Post Divider (When 25MHz crystal used). 1/2/3/4. 15:13 / / / 12:8 R/W 0x18 PLL_FACTOR_N. PLL Factor N. Factor=0, N=1 Factor=1, N=2 Factor=2, N=3 …… Factor=31, N=32 7:6 / / / 5:4 R/W 0x1 PLL_FACTOR_K. PLL Factor K.(K=Factor + 1 ) The range is from 1 to 4. 3:2 / / / 1:0 R/W 0x1 PLL_FACTOR_M. PLL Factor M (M = Factor + 1) is only valid in plltest debug.
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System R/W 0x1 PLL_MODE_SEL. 0: Fractional Mode 1: Integer Mode Note: When in Fractional mode, the Pre Divider M should be set to 0. 23:21 / / / 20 R/W 0x0 PLL_SDM_EN. 0: Disable 1: Enable 19:15 / / / 14:8 R/W 0x62 PLL_FACTOR_N PLL Factor N. Factor=0, N=1 Factor=1, N=2 Factor=2, N=3 …… Factor=0x7F, N=128 7:4 / / / 3:0 R/W 0x7 PLL_PRE_DIV_M. PLL Per Divider (M = Factor+1). The range is from 1 to 16. id e nt ia l 24 4.3.5.10.
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System 00: /1 01: /2 10: /3 11: /4 4.3.5.11. AHB1/APB1 Configuration Register (Default Value: 0x00001010) Offset: 0x0054 Register Name: AHB1_APB1_CFG_REG R/W Default/Hex Description 31:14 / / / 13:12 R/W 0x1 AHB1_CLK_SRC_SEL. 00: LOSC 01: OSC24M 10: AXI 11: PLL_PERIPH0/ AHB1_PRE_DIV 11:10 / / / 9:8 R/W 0x0 APB1_CLK_RATIO. APB1 Clock Divide Ratio. APB1 clock source is AHB1 clock.
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System APB2 Clock Source Select 00: LOSC 01: OSC24M 1X: PLL_PERIPH0 This clock is used for some special module apbclk(UART、TWI). Because these modules need special clock rate even if the apb1clk changed. / / / 17:16 R/W 0x0 CLK_RAT_N Clock Pre Divide Ratio (n) The select clock source is pre-divided by 2^n. The divider is 1/2/4/8. 15:5 / / / 4:0 R/W 0x0 CLK_RAT_M. Clock Divide Ratio (m) The Pre Divide clock is divided by (m+1). The divider M is from 1 to 32. ia l 23:18 Offset: 0x005C nt 4.
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System R/W 0x0 USB OTG_OHCI0_GATING. Gating Clock for USB OTG_OHCI0 0: Mask 1: Pass 27 R/W 0x0 USBEHCI3_GATING. Gating Clock For USB EHCI3 0: Mask 1: Pass 26 R/W 0x0 USBEHCI2_GATING. Gating Clock For USB EHCI2 0: Mask 1: Pass 25 R/W 0x0 USBEHCI1_GATING. Gating Clock For USB EHCI1 0: Mask 1: Pass 24 R/W 0x0 USB OTG_EHCI0_GATING. Gating Clock For USB OTG_EHCI0 0: Mask 1: Pass 23 R/W 0x0 USB OTG_Device_GATING.
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System / / / 14 R/W 0x0 DRAM_GATING. Gating Clock For DRAM 0: Mask 1: Pass 13 R/W 0x0 NAND_GATING. Gating Clock For NAND 0: Mask 1: Pass 12:11 / / / 10 R/W 0x0 MMC2_GATING. Gating Clock For MMC2 0: Mask 1: Pass 9 R/W 0x0 MMC1_GATING. Gating Clock For MMC1 0: Mask 1: Pass 8 R/W 0x0 MMC0_GATING. Gating Clock For MMC0 0: Mask 1: Pass 7 / / 6 R/W 0x0 5 R/W 0x0 4:0 / id e nt ia l 16:15 / nf DMA_GATING. Gating Clock For DMA 0: Mask 1: Pass co CE_GATING.
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System R/W 0x0 GPU_GATING. 0: Mask 1: Pass. 19:13 / / / 12 R/W 0x0 DE_GATING. 0: Mask 1: Pass. 11 R/W 0x0 HDMI_GATING. 0: Mask 1: Pass. 10 / / / 9 R/W 0x0 TVE_GATING. Gating Clock For TVE 0: Mask 1: Pass. 8 R/W 0x0 CSI_GATING. 0: Mask 1: Pass. 7:6 / / / 5 R/W 0x0 DEINTERLACE_GATING. Gating Clock For DEINTERLACE 0: Mask 1: Pass 4 R/W 0x0 3 R/W 0x0 2:1 / / / 0 R/W 0x0 VE_GATING. Gating Clock For VE 0: Mask 1: Pass. id e nt ia l 20 nf TCON1_GATING.
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System 0: Mask 1: Pass. R/W 0x0 I2S/PCM 1_GATING. Gating Clock For I2S/PCM 1 0: Mask 1: Pass. 12 R/W 0x0 I2S/PCM 0_GATING. Gating Clock For I2S/PCM 0 0: Mask 1: Pass. 11:9 / / / 8 R/W 0x0 THS_GATING. Gating Clock For THS 0: Mask 1: Pass 7:6 / / / 5 R/W 0x0 PIO_GATING. Gating Clock For PIO 0: Mask 1: Pass. 4:2 / / / 1 R/W 0x0 0 R/W 0x0 id e nt ia l 13 nf OWA_GATING. Gating Clock For OWA 0: Mask 1: Pass. co AC_DIG_GATING. Gating Clock For AC Digital 0: Mask 1: Pass 4.
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System Gating Clock For UART2 0: Mask 1: Pass. R/W 0x0 UART1_GATING. Gating Clock For UART1 0: Mask 1: Pass. 16 R/W 0x0 UART0_GATING. Gating Clock For UART0 0: Mask 1: Pass. 15:3 / / / 2 R/W 0x0 TWI2_GATING. Gating Clock For TWI2 0: Mask 1: Pass. 1 R/W 0x0 TWI1_GATING. Gating Clock For TWI1 0: Mask 1: Pass. 0 R/W 0x0 TWI0_GATING. Gating Clock For TWI0 0: Mask 1: Pass. nf id e nt ia l 17 Offset: 0x0070 Bit R/W 31:8 / 7 co 4.3.5.18.
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System 4.3.5.19. THS Clock Register (Default Value: 0x00000000) Offset: 0x0074 Register Name: THS_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock. 0: Clock is OFF 1: Clock is ON This special clock = Clock Source/CLK_DIV_RATIO. 30:26 / / / 25:24 R/W 0x0 THS_CLK_SRC_SEL. Clock Source Select 00: OSC24M 01: / 10: / 11: / 23:2 / / / 1:0 R/W 0x0 THS_CLK_DIV_RATIO. THS clock divide ratio.
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System 00: /1 01: /2 10: /4 11: /8. 15:4 / / / 3:0 R/W 0x0 CLK_DIV_RATIO_M Clock Divide Ratio (m) The pre-divided clock is divided by (m+1). The divider M is from 1 to 16. 4.3.5.21. SDMMC0 Clock Register (Default Value: 0x00000000) Offset: 0x0088 Register Name: SDMMC0_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON. SCLK = Clock Source/Divider N/Divider M. 30:26 / / / 25:24 R/W 0x0 CLK_SRC_SEL.
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System Clock Divide Ratio (m) The pre-divided clock is divided by (m+1). The divider M is from 1 to 16. 4.3.5.22. SDMMC1 Clock Register (Default Value: 0x00000000) Offset: 0x008C Register Name: SDMMC1_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON. If SDMMC1 is in old mode, SCLK = Clock Source/Divider N/Divider M. If SDMMC1 is in new mode, SCLK= Clock Source/Divider N/Divider M/2. 30 R/W 0x0 MMC1_MODE_SELECT.
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System 4.3.5.23. SDMMC2 Clock Register (Default Value: 0x00000000) Offset: 0x0090 Register Name: SDMMC2_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON. If SDMMC2 is in old mode, SCLK = Clock Source/Divider N/Divider M. If SDMMC2 is in new mode, SCLK= Clock Source/Divider N/Divider M/2. 30 R/W 0x0 MMC2_MODE_SELECT. 0: Old Mode 1: New Mode. 29:26 / / / 25:24 R/W 0x0 CLK_SRC_SEL.
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System 4.3.5.24. TS Clock Register (Default Value: 0x00000000) Offset: 0x0098 Register Name: TS_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON. SCLK = Clock Source/Divider N/Divider M. 30:28 / / / 27:24 R/W 0x0 CLK_SRC_SEL. Clock Source Select 0000: OSC24M 0001: PLL_PERIPH0 Others: / 23:18 / / / 17:16 R/W 0x0 CLK_DIV_RATIO_N. Clock pre-divide ratio (n) The select clock source is pre-divided by 2^n.
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System 00: /1 01: /2 10: /4 11: /8. 15:4 / / / 3:0 R/W 0x0 CLK_DIV_RATIO_M. Clock divide ratio (m) The pre-divided clock is divided by (m+1). The divider M is from 1 to 16. 4.3.5.26. SPI0 Clock Register (Default Value: 0x00000000) Offset: 0x00A0 Register Name: SPI0_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON. SCLK = Clock Source/Divider N/Divider M. 30:26 / / / 25:24 R/W 0x0 CLK_SRC_SEL.
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System Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON. SCLK= Clock Source/Divider N/Divider M. / / / 25:24 R/W 0x0 CLK_SRC_SEL. Clock Source Select 00: OSC24M 01: PLL_PERIPH0 10: PLL_PERIPH1 11: / 23:18 / / / 17:16 R/W 0x0 CLK_DIV_RATIO_N. Clock Pre Divide Ratio (n) 00: /1 01: /2 10: /4 11: /8. 15:4 / / / 3:0 R/W 0x0 CLK_DIV_RATIO_M. Clock Divide Ratio (m) The pre-divided clock is divided by (m+1). The divider M is from 1 to 16. id e nt ia l 30:26 nf 4.3.
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System 4.3.5.29. I2S/PCM 1 Clock Register (Default Value: 0x00000000) Offset: 0x00B4 Register Name: I2S/PCM 1_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock(Max Clock = 200MHz) 0: Clock is OFF 1: Clock is ON. 30:18 / / / 17:16 R/W 0x0 CLK_SRC_SEL.
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System 3:0 R/W 0x0 CLK_DIV_RATIO_M. Clock Divide Ratio (m) The pre-divided clock is divided by (m+1). The divider M is from 1 to 16. 4.3.5.32. USBPHY Configuration Register (Default Value: 0x00000000) Offset: 0x00CC Register Name: USBPHY_CFG_REG R/W Default/Hex Description 31:20 / / / 19 R/W 0x0 SCLK_GATING_OHCI3. Gating Special Clock For OHCI3 0: Clock is OFF 1: Clock is ON 18 R/W 0x0 SCLK_GATING_OHCI2.
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System USB PHY3 Reset Control 0: Assert 1: De-assert R/W 0x0 USBPHY2_RST. USB PHY2 Reset Control 0: Assert 1: De-assert. 1 R/W 0x0 USBPHY1_RST. USB PHY1 Reset Control 0: Assert 1: De-assert 0 R/W 0x0 USBPHY0_RST. USB PHY0 Reset Control 0: Assert 1: De-assert ia l 2 Register Name: DRAM_CFG_REG R/W Default/Hex 31 R/W 0x0 21:20 R/W 0x0 19:17 / 16 DRAM_CTR_RST. DRAM Controller Reset For AHB Clock Domain. 0: Assert 1: De-assert. CLK_SRC_SEL.
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System 4.3.5.34. MBUS Reset Register (Default Value: 0x80000000) Offset: 0x00FC Bit R/W 31 R/W 30:0 / Register Name: MBUS_RST_REG Default/Hex 0x1 Description MBUS_RESET. 0: Reset Mbus Domain 1: Assert Mbus Domain. / / 4.3.5.35. DRAM Clock Gating Register (Default Value: 0x00000000) Offset: 0x0100 Register Name: DRAM_CLK_GATING_REG R/W Default/Hex Description 31:4 / / / 3 R/W 0x0 TS_DCLK_GATING. Gating DRAM Clock For TS 0: Mask 1: Pass 2 R/W 0x0 DEINTERLACE_DCLK_GATING.
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System Clock Source Select 000: PLL_PERIPH0(2X) 001: PLL_DE Others: / 23:4 / / / 3:0 R/W 0x0 CLK_DIV_RATIO_M. Clock Divide Ratio (m) The pre-divided clock is divided by (m+1). The divider is from 1 to 16. 4.3.5.37. TCON0 Clock Register (Default Value: 0x00000000) Register Name: TCON0_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock 0: Clock is OFF 1: Clock is ON. 30:27 / / / 26:24 R/W 0x0 CLK_SRC_SEL. Clock Source Select 000: PLL_VIDEO Others: /.
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System 23:4 / / / 3:0 R/W 0x0 CLK_DIV_RATIO_M. Clock Divide Ratio (m) The pre-divided clock is divided by (m+1). The divider is from 1 to 16. 4.3.5.39. DEINTERLACE Clock Register (Default Value: 0x00000000) Offset: 0x0124 Register Name: DEINTERLACE_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock 0: Clock is OFF 1: Clock is ON SCLK = Clock Source/ Divider M 30:27 / / / 26:24 R/W 0x0 CLK_SRC_SEL.
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System 0: Clock is OFF 1: Clock is ON. SCLK= Special Clock Source/CSI_SCLK_DIV_M. / / / 26:24 R/W 0x0 SCLK_SRC_SEL. Special Clock Source Select 000: PLL_PERIPH0 001: PLL_PERIPH1 Others: / 23:20 / / / 19:16 R/W 0x0 CSI_SCLK_DIV_M. CSI Clock Divide Ratio (m) The pre-divided clock is divided by (m+1). The divider M is from 1 to 16. 15 R/W 0x0 CSI_MCLK_GATING. Gating Master Clock 0: Clock is OFF 1: Clock is ON This clock =Master Clock Source/ CSI_MCLK_DIV_M.
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System 4.3.5.43. AC Digital Clock Register (Default Value: 0x00000000) Offset: 0x0140 Register Name: AC_DIG_CLK_REG Bit R/W Default/Hex Description 31 R/W 0x0 SCLK_1X_GATING. Gating Special Clock 0: Clock is OFF 1: Clock is ON SCLK = PLL_AUDIO Output. 30:0 / / / Offset: 0x0144 ia l 4.3.5.44. AVS Clock Register (Default Value: 0x00000000) Register Name: AVS_CLK_REG R/W Default/Hex Description 31 R/W 0x0 SCLK_GATING. Gating Special Clock 0: Clock is OFF 1: Clock is ON. SCLK= OSC24M.
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System 4.3.5.46. HDMI Slow Clock Register (Default Value: 0x00000000) Offset: 0x0154 Register Name: HDMI_SLOW_CLK_REG Bit R/W Default/Hex Description 31 R/W 0x0 HDMI_DDC_CLK_GATING. 0: Clock is OFF 1: Clock is ON. SCLK = OSC24M. 30:0 / / / Offset: 0x015C Register Name: MBUS_CLK_REG R/W Default/Hex Description MBUS_SCLK_GATING. Gating Clock for MBUS 0: Clock is OFF 1: Clock is ON. MBUS_CLOCK = Clock Source/Divider M 31 R/W 0x0 30:26 / / id e nt Bit ia l 4.3.5.47.
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System 30:3 / / /. 2:0 R/W 0x0 CLK_DIV_RATIO_N. Clock Pre Divide Ratio (N) The select clock source is pre-divided by( n+1). The divider N is from 1 to 8. 4.3.5.49. PLL Stable Time Register0 (Default Value: 0x000000FF) Offset: 0x0200 Register Name: PLL_STABLE_TIME_REG0 R/W Default/Hex Description 31:16 / / / 15:0 R/W 0x00FF PLL_LOCK_TIME PLL Lock Time (Unit: us).
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System 10:8 R/W 0x2 PLL_LOCK_CTRL. PLL Lock Time Control[2:0]. 7:4 / / / 3:0 R/W 0x0 PLL_DAMP_FACT_CTRL. PLL Damping Factor Control[3:0]. 4.3.5.52. PLL_AUDIO Bias Register (Default Value: 0x10100000) Offset: 0x0224 Register Name: PLL_AUDIO_BIAS_REG R/W Default/Hex Description 31:29 / / / 28:24 R/W 0x10 PLL_VCO_BIAS. PLL VCO Bias Current[4:0]. 23:21 / / / 20:16 R/W 0x10 PLL_BIAS_CUR. PLL Bias Current[4:0]. 15:0 / / / nt ia l Bit Offset: 0x0228 id e 4.3.5.53.
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System 20:16 R/W 0x10 PLL_BIAS_CTRL. PLL Bias Control[4:0]. 15:3 / / / 2:0 R/W 0x0 PLL_DAMP_FACTOR_CTRL. PLL Damping Factor Control[2:0]. 4.3.5.55. PLL_DDR Bias Register (Default Value: 0x81104000) Offset: 0x0230 Register Name: PLL_DDR_BIAS_REG R/W Default/Hex Description 31:28 R/W 0x8 PLL_VCO_BIAS. PLL VCO Bias[3:0]. 27:26 / / /. 25 R/W 0x0 PLL_VCO_GAIN_CTRL_EN. PLL VCO Gain Control Enable. 0: Disable 1: Enable. 24 R/W 0x1 PLL_BANDW_CTRL. PLL Band Width Control.
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System 4 R/W 0x1 PLL_BANDW_CTRL. PLL Band Width Control. 0: Narrow 1: Wide 3:2 / / / 1:0 R/W 0x0 PLL_DAMP_FACTOR_CTRL. PLL Damping Factor Control[1:0]. 4.3.5.57. PLL_GPU Bias Register (Default Value: 0x10100000) Offset: 0x023C Register Name: PLL_GPU_BIAS_REG R/W Default/Hex Description 31:29 / / / 28:24 R/W 0x10 PLL_VCO_BIAS_CTRL. PLL VCO Bias Control[4:0]. 23:21 / / / 20:16 R/W 0x10 PLL_BIAS_CTRL. PLL Bias Control[4:0]. 15:3 / / / 2:0 R/W 0x0 PLL_DAMP_FACTOR_CTRL.
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System 4.3.5.59. PLL_DE Bias Register (Default Value: 0x10100000) Offset: 0x0248 Register Name: PLL_DE_BIAS_REG R/W Default/Hex Description 31:29 / / / 28:24 R/W 0x10 PLL_VCO_BIAS_CTRL. PLL VCO Bias Control[4:0]. 23:21 / / / 20:16 R/W 0x10 PLL_BIAS_CTRL. PLL Bias Control[4:0]. 15:3 / / / 2:0 R/W 0x0 PLL_DAMP_FACTOR_CTRL. PLL Damping Factor Control[2:0]. ia l Bit 4.3.5.60.
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System 4.3.5.61. PLL_DDR Tuning Register (Default Value: 0x14880000) Offset: 0x0260 Register Name: PLL_DDR_TUN_REG R/W Default/Hex Description 31:29 / / / 28 R/W 0x1 VREG1_OUT_EN. Vreg1 Out Enable. 0: Disable 1: Enable 27 / / / 26:24 R/W 0x4 PLL_LTIME_CTRL. PLL Lock Time Control[2:0]. 23 R/W 0x0 VCO_RST. VCO Reset In. 22:16 R/W 0x10 PLL_INIT_FREQ_CTRL. PLL Initial Frequency Control[6:0]. 15 R/W 0x0 OD1. Reg-Od1 For Verify. 14:8 R/W 0x10 B_IN. B-In[6:0] For Verify.
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System 10: 32.5KHz 11: 33KHz 16:0 R/W 0x0 WAVE_BOT. Wave Bottom. 4.3.5.63. PLL_AUDIO Pattern Control Register(Default Value: 0x00000000) Offset: 0x0284 Register Name: PLL_AUDIO_PAT_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 SIG_DELT_PAT_EN. Sigma-delta Pattern Enable. 30:29 R/W 0x0 SPR_FREQ_MODE. Spread Frequency Mode. 00: DC=0 01: DC=1 1X: Triangular 28:20 R/W 0x0 WAVE_STEP. Wave Step. 19 / / / 18:17 R/W 0x0 FREQ. Frequency. 00: 31.5KHz 01: 32KHz 10: 32.
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System 18:17 R/W 0x0 FREQ. Frequency. 00: 31.5KHz 01: 32KHz 10: 32.5KHz 11: 33KHz 16:0 R/W 0x0 WAVE_BOT. Wave Bottom. 4.3.5.65. PLL_VE Pattern Control Register (Default Value: 0x00000000) Offset: 0x028C Register Name: PLL_VE_PAT_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 SIG_DELT_PAT_EN. Sigma-delta Pattern Enable. 30:29 R/W 0x0 SPR_FREQ_MODE. Spread Frequency Mode. 00: DC=0 01: DC=1 1X: Triangular 28:20 R/W 0x0 WAVE_STEP. Wave Step.
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System 28:20 R/W 0x0 WAVE_STEP. Wave step. 19 / / / 18:17 R/W 0x0 FREQ. Frequency. 00: 31.5KHz 01: 32KHz 10: 32.5KHz 11: 33KHz 16:0 R/W 0x0 WAVE_BOT. Wave Bottom. Offset: 0x029C ia l 4.3.5.67. PLL_GPU Pattern Control Register (Default Value: 0x00000000) Register Name: PLL_GPU_PAT_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 SIG_DELT_PAT_EN. Sigma-Delta Pattern Enable. 30:29 R/W 0x0 SPR_FREQ_MODE. Spread Frequency Mode.
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System Spread Frequency Mode. 00: DC=0 01: DC=1 1X: Triangular R/W 0x0 WAVE_STEP. Wave Step. 19 / / / 18:17 R/W 0x0 FREQ. Frequency. 00: 31.5KHz 01: 32KHz 10: 32.5KHz 11: 33KHz 16:0 R/W 0x0 WAVE_BOT. Wave Bottom. ia l 28:20 Register Name: PLL_DE_PAT_CTRL_REG Bit R/W Default/Hex 31 R/W 0x0 30:29 R/W 0x0 28:20 R/W 19 / 18:17 16:0 Description id e Offset: 0x02A8 nt 4.3.5.69. PLL_DE Pattern Control Register (Default Value: 0x00000000) SIG_DELT_PAT_EN.
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R/W Default/Hex Description 31 R/W 0x0 USBOHCI3_RST. USB OHCI3 Reset Control 0: Assert 1: De-assert 30 R/W 0x0 USBOHCI2_RST. USB OHCI2 Reset Control 0: Assert 1: De-assert 29 R/W 0x0 USBOHCI1_RST. USB OHCI1 Reset Control 0: Assert 1: De-assert 28 R/W 0x0 USB OTG_OHCI0_RST. USB OTG_OHCI0 Reset Control 0: Assert 1: De-assert 27 R/W 0x0 USBEHCI3_RST. USB EHCI3 Reset Control 0: Assert 1: De-assert 26 R/W 0x0 25 R/W 0x0 24 R/W 23 nt ia l Bit id e System nf USBEHCI2_RST.
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System R/W 0x0 HSTMR_RST. HSTMR Reset. 0: Assert 1: De-assert 18 R/W 0x0 TS_RST. TS Reset. 0: Assert 1: De-assert 17 R/W 0x0 EMAC_RST. EMAC Reset. 0: Assert 1: De-assert 16:15 / / / 14 R/W 0x0 SDRAM_RST. SDRAM AHB Reset. 0: Assert 1: De-assert 13 R/W 0x0 NAND_RST. NAND Reset. 0: Assert 1: De-assert 12:11 / / 10 R/W 0x0 9 R/W 0x0 8 R/W 0x0 SD0_RST. SD/MMC0 Reset. 0: Assert 1: De-assert 7 / / / 6 R/W 0x0 DMA_RST. DMA Reset.
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System 4.3.5.71. Bus Software Reset Register 1 (Default Value: 0x00000000) Register Name: BUS_SOFT_RST_REG1 R/W Default/Hex Description 31 R/W 0x0 DBGSYS_RST. DBGSYS Reset. 0: Assert 1: De-assert 30:23 / / / 22 R/W 0x0 SPINLOCK_RST. SPINLOCK Reset. 0: Assert 1: De-assert. 21 R/W 0x0 MSGBOX_RST. MSGBOX Reset. 0: Assert 1: De-assert. 20 R/W 0x0 GPU_RST. GPU Reset. 0: Assert 1: De-assert. 19:13 / / 12 R/W 0x0 11 R/W 10 id e nt Bit ia l Offset: 0x02C4 / co nf DE_RST.
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R/W 0x0 DEINTERLACE_RST. DEINTERLACE Reset. 0: Assert 1:De-assert 4 R/W 0x0 TCON1_RST. TCON1 Reset. 0: Assert 1: De-assert. 3 R/W 0x0 TCON0_RST. TCON0 Reset. 0: Assert 1: De-assert. 2:1 / / / 0 R/W 0x0 VE_RST. VE Reset. 0: Assert 1: De-assert. nt 5 ia l System Offset: 0x02C8 id e 4.3.5.72. Bus Software Reset Register 2 (Default Value: 0x00000000) Register Name: BUS_SOFT_RST_REG2 Bit R/W Default/Hex 31:3 / / 2 R/W 0x0 1:0 / Description / co nf EPHY_RST. EPHY Reset.
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System / / / 8 R/W 0x0 THS_RST. THS Reset. 0: Assert 1: De-assert 7:2 / / / 1 R/W 0x0 OWA_RST. OWA Reset. 0: Assert 1: De-assert 0 R/W 0x0 AC_RST. AC Reset. 0: Assert 1: De-assert nt 11:9 ia l I2S/PCM 0 Reset. 0: Assert 1: De-assert. Offset: 0x02D8 id e 4.3.5.74. Bus Software Reset Register 4 (Default Value: 0x00000000) Register Name: BUS_SOFT_RST_REG4 Bit R/W Default/Hex 31:21 / / 20 R/W 0x0 19 R/W 18 Description / co nf SCR_RST. SCR Reset.
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System 2 R/W 0x0 TWI2_RST. TWI2 Reset. 0: Assert 1: De-assert. 1 R/W 0x0 TWI1_RST. TWI1 Reset. 0: Assert 1: De-assert. 0 R/W 0x0 TWI0_RST. TWI0 Reset. 0: Assert 1: De-assert. Offset: 0x02F0 ia l 4.3.5.75.
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System R/W Default/Hex Description 31:8 / / / 7 R/W 0x0 DET_FIN. Detect Finish. 0: Unfinished 1: Finished Set 1 to this bit will clear it. 6 R/W 0x0 DLY_SEL. Delay Select 0: 1 Cycle 1: 2 Cycles 5:4 R/W 0x0 OSC_SEL OSC Select. 00: IDLE 01: SVT 10: LVT 11: ULVT 3:1 R/W 0x0 TIME_DET. Time detect. 000: 0.5/4 us 001: 0.5/2 us 002: 0.5/1 us 003: 0.5*2us ................. 111:0.5*2^5us 0 R/W 0x0 id e nt ia l Bit co nf MOD_EN. Module enable. 0: Disable 1: Enable 4.3.5.77.
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System 4.3.6. Programming Guidelines 4.3.6.1. PLL 1) 2) In practical application, other PLLs doesn’t support dynamic frequency scaling except for PLL_CPUX; After the PLL_DDR frequency changes, the 20-bit of PLL_DDR Control Register should be written 1 to make it valid; 4.3.6.2. BUS ia l 1) When setting the BUS clock , you should set the division factor first, and after the division factor becomes valid, switch the clock source.
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System 4.4. CPU Configuration 4.4.1. Overview CPUCFG module is used to configure related CPU parameters.
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System 4.4.3. Register Description 4.4.3.1. CPUS Reset Control Register(Default Value: 0x00000000) Offset: 0x00 Register Name: CPUS_RST_CTRL_REG Bit R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 CPUS_RESET. CPUS Reset Assert. 0: assert 1: de-assert. Offset: 0x40 ia l 4.4.3.2. CPU0 Reset Control Register(Default Value: 0x00000000) Register Name: CPU0_RST_CTRL_REG R/W Default/Hex Description 31:2 / / / 1 R/W 0x1 CPU0_CORE_REST.
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System 4.4.3.4. CPU0 Status Register (Default Value: 0x00000000) Offset: 0x48 Register Name: CPU0_STATUS_REG R/W Default/Hex Description 31:3 / / / 2 R 0x0 STANDBYWFI. Indicates if the processor is in WFI standby mode: 0: Processor not in WFI standby mode. 1: Processor in WFI standby mode 1 R 0x0 STANDBYWFE.
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System Disable write access to certain CP15 registers. 0: enable 1: disable 4.4.3.7. CPU1 Status Register(Default Value: 0x00000000) Offset: 0x88 Register Name: CPU1_STATUS_REG R/W Default/Hex Description 31:3 / / /. 2 R 0x0 STANDBYWFI. Indicates if the processor is in WFI standby mode: 0: Processor not in WFI standby mode. 1: Processor in WFI standby mode 1 R 0x0 STANDBYWFE.
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System 4.4.3.9. CPU2 Control Register(Default Value: 0x00000000) Offset: 0xC4 Register Name: CPU2_CTRL_REG Bit R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 CPU2_CP15_WRITE_DISABLE. Disable write access to certain CP15 registers. 0: enable 1: disable 4.4.3.10. CPU2 Status Register(Default Value: 0x00000000) Offset: 0xC8 Register Name: CPU2_STATUS_REG R/W Default/Hex Description 31:3 / / /. 2 R 0x0 STANDBYWFI.
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System domains. They do not reset debug logic in the debug power domain. 0: assert 1: de-assert. 4.4.3.12. CPU3 Control Register(Default Value: 0x00000000) Offset: 0x104 Register Name: CPU3_CTRL_REG R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 CPU3_CP15_WRITE_DISABLE. Disable write access to certain CP15 registers. 0: enable 1: disable Offset: 0x108 nt 4.4.3.13.
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System 4.4.3.15. CPU Clock Gating Register(Default Value: 0x0000010F) Offset: 0x144 Register Name: CPU_CLK_GATING_REG R/W Default/Hex Description 31:9 / / / 8 R/W 0x1 L2_CLK_GATING L2 Clock gating 0: clock off 1: clock on 7:4 / / / 3:0 R/W 0xF CPU_CLK_GATING CPU0/1/2/3 Clock gating 0: clock off 1: clock on Offset: 0x184 nt 4.4.3.16. General Control Register(Default Value: 0x00000020) ia l Bit Register Name: GENER_CTRL_REG R/W Default/Hex Description 31:9 / / /.
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System 31:16 R/W 0x0 SUP_STANDBY_FLAG. Key Field. Any value can be written and read back in the key field, but if the values are not appropriate, the lower 16 bits will not change in this register. Only fellow the appropriate process, the super standby flag can be written in the lower 16 bits. Refer to Description and Diagram. 15:0 R/W 0x0 SUP_STANBY_FLAG_DATA. Refer to Description and Diagram Note: When system is turned on, the value in the Super Standby Flag Register low 16 bits should be 0x0.
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System 4.4.3.20. 64-bit Counter High Register(Default Value: 0x00000000) Offset: 0x288 Register Name: CNT64_High_REG R/W Default/Hex Description 31:0 R/W 0x0 CNT64_LO. 64-bit Counter [63:32]. co nf id e nt ia l Bit H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System 4.5. System Control Area Size(Bytes) A1 64K A2 32K CPUX I-Cache 32K (X=0,1,2,3) CPUX D-Cache 32K (X=0,1,2,3) CPU L2 Cache 512K Total 864K 4.5.2. ia l Overview System Control Register List nt 4.5.1. Base Address System Control 0x01C00000 id e Module Name Register Name VER_REG 0x24 Version Register 0x30 EMAC-EPHY Clock Register System Control Register Description co 4.5.3. Description nf EMAC_EPHY_CLK_REG Offset 4.5.3.1.
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System 4.5.3.2.
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System 1: Enable R/W 0x0 ETXIE Enable EMAC Transmit Clock Invertor. 0: Disable 1: Enable 2 R/W 0x0 EPIT EMAC PHY Interface Type 0: MII 1: RGMII 1:0 R/W 0x0 ETCS. EMAC Transmit Clock Source 00: Transmit clock source for MII 01: External transmit clock source for GMII and RGMII 10: Internal transmit clock source for GMII and RGMII 11: Reserved co nf id e nt ia l 3 H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System 4.6. Timer 4.6.1. Overview Timer 0/1 can take their inputs from Internal OSC or OSC24M. They provide the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long or short response time. They provide 24-bit programmable overflow counter and work in auto-reload mode or no-reload mode. When the current value in Current Value Register is counting down to zero, the timer will generate interrupt if set interrupt enable bit.
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System 4.6.3.
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System 4.6.4.2. Timer IRQ Status Register (Default Value: 0x00000000) Offset:0x04 Bit Register Name: TMR_IRQ_STA_REG R/W 31:2 / Default/Hex Description / / R/W 0x0 TMR1_IRQ_PEND. Timer 1 IRQ Pending. Set 1 to the bit will clear it. 0: No effect; 1: Pending, timer 1 interval value is reached. 0 R/W 0x0 TMR0_IRQ_PEND. Timer 0 IRQ Pending. Set 1 to the bit will clear it. 0: No effect; 1: Pending, timer 0 interval value is reached. 4.6.4.3.
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System Timer 0 Reload. 0: No effect 1: Reload timer 0 Interval value. After the bit is set, it can not be written again before it’s cleared automatically. R/W 0x0 TMR0_EN. Timer 0 Enable. 0: Stop/Pause 1: Start. When the timer is started, it will reload the interval value to internal register, and the current counter will count from interval value to 0. If the current counter does not reach the zero, the timer enable bit is set to “0”, the current value counter will pause.
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System automatically. 1: Single mode. When interval value reached, the timer will disable automatically. R/W 0x0 TMR1_CLK_PRES. Select the pre-scale of timer 1 clock source. 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 3:2 R/W 0x1 TMR1_CLK_SRC. 00: Internal OSC / N 01: OSC24M. 10: / 11: /. Internal OSC / N is about 32KHz. 1 R/W 0x0 TMR1_RELOAD. Timer 1 Reload. 0: No effect 1: Reload timer 1 Interval value.
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System Timer 1 Interval Value. Note: The value setting should consider the system clock and the timer clock source. 4.6.4.8. Timer 1 Current Value Register Offset:0x28 Register Name: TMR1_CUR_VALUE_REG Bit R/W Default/Hex Description 31:0 R/W 0x0 TMR1_CUR_VALUE. Timer 1 Current Value. Note: Timer1 current value is a 32-bit down-counter (from interval value to 0). Offset:0x80 ia l 4.6.4.9.
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System the internal 33-bits counter register can be set by software. The LSB bit of the 33-bits counter register should be zero when the initial value is updated. It will count from the initial value. The initial value can be updated at any time. It can also be paused by setting AVS_CNT0_PS to ‘1’. When it is paused, the counter won’t increase. 4.6.4.11. AVS Counter 1 Register (Default Value: 0x00000000) Offset:0x88 Register Name: AVS_CNT1_REG R/W Default/Hex Description 31:0 R/W 0x0 AVS_CNT1.
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System The 12-bits counter is used for counting the cycle number of one 24Mhz clock. When the 12-bits counter reaches (>= N) the divisor value, the internal 33-bits counter register will increase 1 and the 12-bits counter will reset to zero and restart again. Note: It can be configured by software at any time. 4.6.4.13. Watchdog0 IRQ Enable Register (Default Value: 0x00000000) Offset:0xA0 Register Name: WDOG0_IRQ_EN_REG R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 WDOG0_IRQ_EN.
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System 4.6.4.16. Watchdog0 Configuration Register (Default Value: 0x00000001) Offset:0xB4 Register Name: WDOG0_CFG_REG Bit R/W Default/Hex Description 31:2 / / / 1:0 R/W 0x1 WDOG0_CONFIG. Watchdog0 generates a reset signal 00: / 01: To whole system 10: Only interrupt 11: / Offset:0xB8 ia l 4.6.4.17. Watchdog0 Mode Register (Default Value: 0x00000000) Register Name: WDOG0_MODE_REG R/W Default/Hex Description 31:8 / / / 7:4 R/W 0x0 WDOG0_INTV_VALUE.
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System 4.6.5. Programming Guidelines 4.6.5.1. Timer Take making a Timer0 1ms delay for an example, 24M clock source, single mode and 2 pre-scale will be selected in the instance. //Set interval value //Select Single mode,24MHz clock source,2 pre-scale //Set Reload bit //Waiting Reload bit turns to 0 //Enable Timer0 ia l writel(0x2EE0,TMR_0_INTV); writel(0x94, TMR_0_CTRL); writel(readl(TMR_0_CTRL)|(1<<1), TMR_0_CTRL); while((readl(TMR_0_CTRL)>>1)&1); writel(readl(TMR_0_CTRL)|(1<<0), TMR_0_CTRL); 4.6.5.
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System 4.7. Trusted Watchdog 4.7.1. Overview The trusted watchdog is primarily used to protect the trusted world operations from denial of service when secure services are dependent to the RichOS scheduler. For example, if the trusted world is not entered after a defined time limit the SoC is re-started to perform an authentication of the system. The trusted watchdog can also be used to mask the real cause of a security error thanks to the delayed warm reset it generates. Block Diagram ia l 4.7.2.
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System Clock sources driving the watchdog timer must be controlled or managed by a trusted entity. This means that non-trusted world accesses are not permitted to turn on, turn off or modify the characteristics of clock source. The Clear Enable will reset relevant bits in the watchdog registers, except the reset flag. 4.7.3.2. NV-Counter 4.7.4.
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System 4.7.5. TWD Register Description 4.7.5.1. TWD Status Register (Default Value: 0x00000000) Offset: 0x0000 Register Name: TWD_STATUS_REG Bit R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 TWD_PEND_FLAG. Interrupt pending. Set 1 to the bit will clear it. 0: No effect. 1: Pending. Offset: 0x0010 ia l 4.7.5.2. TWD Control Register (Default Value: 0x00000000) Register Name: TWD_CTRL_REG R/W Default/Hex Description 31 R/W 0x0 CNT64_CLK_SRC_SEL. 64-bit counter clock source select.
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System 4.7.5.3. TWD Restart Register (Default Value: 0x00000000) Offset: 0x0014 Register Name: TWD_RESTART_REG R/W Default/Hex Description 31:28 / / / 27:16 WO 0x0 TWD_RESTART_KEYFILED. Should be written at value 0xD14. Writing any other value in this field aborts the write operation. 15:1 / / / 0 WO 0x0 TWD_RESTART_EN. If writing ‘1’ in this bit, the value of Counter Compare Registers would change. 0: No effect. 1: Restart enable. ia l Bit Offset: 0x0020 nt 4.7.5.4.
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System Bit R/W Default/Hex Description 31:0 RO 0x0 TWD_LOW_CMP. The TWD low 32-bit compare counter. 4.7.5.8. TWD High Counter Compare Register (Default Value: 0x00000000) Offset: 0x0044 Register Name: TWD_HIGH_CNT_CMP_REG Bit R/W Default/Hex Description 31:0 RO 0x0 TWD_HIGH_CMP. The TWD high 32-bit compare counter. Offset: 0x0100 ia l 4.7.5.9.
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System This counter is used for synchronizing data stores against replay attacks. 4.7.5.13. Synchronize Data Counter Register 3 (Default Value: 0x00000000) Offset: 0x011C Register Name: SYN_DATA_CNT_REG3 R/W Default/Hex Description 31:0 R/W 0x0 SYN_DATA_CNT3. This counter is used for synchronizing data stores against replay attacks. co nf id e nt ia l Bit H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System 4.8. RTC 4.8.1. Overview The real time clock (RTC) is for calendar usage. It is built around a 30-bit counter and used to count elapsed time in YY-MM-DD and HH-MM-SS. The unit can be operated by the backup battery while the system power is off. It has a built-in leap year generator and a independent power pin (RTC_VIO). ia l The alarm generates an alarm signal at a specified time in the power-off mode or normal operation mode.
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System RTC_DEB_REG 0x170 RTC Debug Register GPL_HOLD_OUTPUT_REG 0x180 GPL Hold Output Register VDD_RTC_REG 0x190 VDD RTC Regulate Register IC_CHARA_REG 0x1F0 IC Characteristic Register 4.8.3. RTC Register Description 4.8.3.1. LOSC Control Register (Default Value: 0x00004000) Offset:0x0 Register Name: LOSC_CTRL_REG R/W Default/Hex Description 31:16 W 0x0 KEY_FIELD. Key Field. This field should be filled with 0x16AA, and then the bit 0 can be written with the new value.
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System 0 R/W 0x0 LOSC_SRC_SEL. LOSC Clock source Select. ‘N’ is the value of Internal OSC Clock Prescalar register. 0: InternalOSC /32/ N, 1: External 32.768KHz OSC. (InternalOSC=16MHz) Note1: Any bit of [9:7] is set, the RTC HH-MM-SS, YY-MM-DD and ALARM DD-HH-MM-SS register can’t be written. Note2: Internal OSC is about 16MHz. 4.8.3.2.
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System R/W Default/Hex Description 31:23 / / / 22 R/W 0x0 LEAP. Leap Year. 0: not, 1: Leap year. This bit can not set by hardware. It should be set or clear by software. 21:16 R/W x YEAR. Year. Range from 0~63. 15:12 / / / 11:8 R/W x MONTH. Month. Range from 1~12. 7:5 / / / 4:0 R/W x DAY. Day. Range from 1~31. ia l Bit id e nt Note1: If the written value is not from 1 to 31 in Day Area, it turns into 31 automatically. Month Area and Year Area are similar to Day Area.
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System Note: If the written value is not from 0 to 59 in Second Area, it turns into 59 automatically. Minute Area and Hour Area are similar to Second Area. 4.8.3.6. Alarm 0 Counter Register (Default Value: 0x00000000) Offset:0x20 Register Name: ALARM0_COUNTER_REG Bit R/W Default/Hex Description 31:0 R/W 0x0 ALARM0_COUNTER. Alarm 0 Counter is Based on Second. ia l Note: If the second is set to 0, it will be 1 second in fact. 4.8.3.7.
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System Alarm 0 IRQ Enable. 0: Disable 1: Enable 4.8.3.10. Alarm 0 IRQ Status Register (Default Value: 0x00000000) Offset:0x30 Register Name: ALARM0_IRQ_STA_REG R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 ALARM0_IRQ_PEND. Alarm 0 IRQ Pending bit. 0: No effect 1: Pending, alarm 0 counter value is reached If alarm 0 irq enable is set to 1, the pending bit will be sent to the interrupt controller. nt ia l Bit 4.8.3.11.
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System 1: Enable If this bit is set to “1”, only when the Alarm 1 Week HH-MM-SS register valid bits is equal to RTC HH-MM-SS register and the register RTC HH-MM-SS bit [31:29] is 6, the week 6 alarm irq pending bit will be set to “1”. R/W 0x0 WK5_ALM1_EN. Week 5 (Saturday) Alarm 1 Enable.
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System [31:29] is 0, the week 0 alarm irq pending bit will be set to “1”. 4.8.3.13. Alarm 1 IRQ Enable Register (Default Value: 0x00000000) Offset:0x48 Register Name: ALARM1_IRQ_EN Bit R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 ALARM1_IRQ_EN. Alarm 1 IRQ Enable. 0: Disable 1: Enable Offset:0x4C ia l 4.8.3.14. Alarm 1 IRQ Status Register (Default Value: 0x00000000) Register Name: ALARM1_IRQ_STA_REG R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 ALARM1_WEEK_IRQ_PEND.
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System 0 R/W 0x0 LOSC_OUT_GATING. Configuration of LOSC output, and no LOSC output by default. 0: Enable LOSC output gating 1: Disable LOSC output gating 4.8.3.17. General Purpose Register (Default Value: 0x00000000)) Offset:0x100+N *0x4 (N=0~7) Register Name: GP_DATA_REGn Bit R/W Default/Hex Description 31:0 R/W 0x0 GP_DATA. Data [31:0]. Register Name: RTC_DEB_REG Bit R/W Default/Hex 31:2 / / 1 R/W 0x0 0 R/W 0x0 Description id e Offset:0x170 nt 4.8.3.18.
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System 0: Hold disable 1: Hold enable R/W 0x0 GPL9_HOLD_OUTPUT. Hold the output of GPIOL9 when system’s power is changing. The output must be low level (0) or high level (1) or High-Z; any other outputs may not hold on. 0: Hold disable 1: Hold enable 8 R/W 0x0 GPL8_HOLD_OUTPUT. Hold the output of GPIOL8 when system’s power is changing. The output must be low level (0) or high level (1) or High-Z; any other outputs may not hold on. 0: Hold disable 1: Hold enable 7 R/W 0x0 GPL7_HOLD_OUTPUT.
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System Hold the output of GPIOL2 when system’s power is changing. The output must be low level (0) or high level (1) or High-Z; any other outputs may not hold on. 0: Hold disable 1: Hold enable R/W 0x0 GPL1_HOLD_OUTPUT. Hold the output of GPIOL1 when system’s power is changing. The output must be low level (0) or high level (1) or High-Z; any other outputs may not hold on. 0: Hold disable 1: Hold enable 0 R/W 0x0 GPL0_HOLD_OUTPUT. Hold the output of GPIOL0 when system’s power is changing.
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System aborts the write operation. R/W 0x0 ID_DATA. Return 0x16aa only if the KEY_FIELD is set as 0x16aa when read those bits, otherwise return 0x0. co nf id e nt ia l 15:0 H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System 4.9. High-speed Timer 4.9.1. Overview High Speed Timer Clock Source are fixed to AHBCLK, which is much higher than OSC24M. Compared with other timers, High Speed Timer clock source is synchronized with AHB clock, and when the relevant bit in the Control Register is set 1, timer goes into the test mode, which is used to System Simulation. When the current value in both LO and HI Current Value Register are counting down to zero, the timer will generate interrupt if set interrupt enable bit.
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System HS_TMR_CTRL_REG 0x10 HS Timer Control Register HS_TMR_INTV_LO_REG 0x14 HS Timer Interval Value Low Register HS_TMR_INTV_HI_REG 0x18 HS Timer Interval Value High Register HS_TMR_CURNT_LO_REG 0x1C HS Timer Current Value Low Register HS_TMR_CURNT_HI_REG 0x20 HS Timer Current Value High Register 4.9.4. HSTimer Register Description 4.9.4.1.
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System automatically. 1: Single mode. When interval value reached, the timer will disable automatically. R/W 0x0 HS_TMR_CLK Select the pre-scale of the high speed timer clock sources. 000: /1 001: /2 010: /4 011: /8 100: /16 101: / 110: / 111: / 3:2 / / / 1 R/W 0x0 HS_TMR_RELOAD. High Speed Timer Reload. 0: No effect, 1: Reload High Speed Timer Interval Value. 0 R/W 0x0 HS_TMR_EN. High Speed Timer Enable. 0: Stop/Pause, 1: Start.
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System High Speed Timer Interval Value [55:32]. Note:The interval value register is a 56-bit register. When read or write the interval value, the Lo register should be read or write first. And the Hi register should be written after the Lo register. 4.9.4.6. HS Timer Current Value Lo Register Offset:0x1C Register Name: HS_TMR_CURNT_LO_REG Bit R/W Default/Hex Description 31:0 R/W x HS_TMR_CUR_VALUE_LO. High Speed Timer Current Value [31:0]. Offset:0x20 ia l 4.9.4.7.
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System 4.10. PWM 4.10.1. Overview The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its programmable registers. Each channel has a dedicated internal 16-bit up counter. If the counter reaches the value stored in the channel period register, it resets. At the beginning of a count period cycle, the PWMOUT is set to active state and count from 0x0000.The PWM divider divides the clock(24MHz) by 1~4096 according to the pre-scalar bits in the PWM control register.
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System 4.10.4. PWM Register Description 4.10.4.1. PWM Control Register(Default Value: 0x00000000) Offset:0x0 Register Name: PWM_CTRL_REG R/W Default/Hex Description 31:29 / / /. 28 RO 0x0 PWM0_RDY. PWM0 period register ready. 0: PWM0 period register is ready to write, 1: PWM0 period register is busy. 27:10 / / / 9 R/W 0x0 PWM0_BYPASS. PWM CH0 bypass enable. If the bit is set to 1, PWM0’s output is OSC24MHz. 0: disable, 1: enable. 8 R/W 0x0 PWM_CH0_PUL_START.
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System 0011: /360 0100: /480 0101: / 0110: / 0111: / 1000: /12k 1001: /24k 1010: /36k 1011: /48k 1100: /72k 1101: / 1110: / 1111: /1 ia l 4.10.4.2. PWM Channel 0 Period Register(Default Value: 0x00000000) Register Name: PWM_CH0_PERIOD nt Offset:0x4 R/W Default/Hex Description 31:16 R/W x PWM_CH0_ENTIRE_CYS Number of the entire cycles in the PWM clock.
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System 4.11. DMA 4.11.1. Overview There are 12 DMA channels in the chip. Each DMA channel can generate interrupts. According to different pending status, the referenced DMA channel generates corresponding interrupt. And, the configuration information of every DMA channel are storing in the DDR or SRAM. When start a DMA transferring, the DMA Channel Descriptor Address Register contains the address information in the DDR or SRAM, where has the relevance configuration information of the DMA transferring.
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System 4.11.2.2. DRQ Type and Corresponding Relation Table 4-1. DMA DRQ Table Source DRQ Type Destination DRQ Type Module Name Port NO.
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System And, by reading the DMA Status Register, the status of a DMA channel could be known. Reading back the descriptor address register, the value is the link data in the transferring package. If only the value is equal to 0xfffff800, then it can be regarded as NULL, which means the package is the last package in this DMA transmission. Otherwise, the value means the start address of the next package. And, the Descriptor Address Register can be changed during a package transferring.
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System DMA_CUR_DEST_REG DMA_BCNT_LEFT_REG DMA_PARA_REG DMA_FDESC_ADDR_REG DMA_PKG_NUM_REG 0x100+N*0x40+0x14 DMA Channel Current Destination Register (N=0~11) 0x100+N*0x40+0x18 DMA Channel Byte Counter Left Register (N=0~11) 0x100+N*0x40+0x1C DMA Channel Parameter Register (N=0~11) 0x100+N*0x40+0x2C DMA Formar Descriptor Address Register (N=0~11) 0x100+N*0x40+0x30 DMA Package Number Register (N=0~11) 4.11.4. DMA Register Description ia l 4.11.4.1.
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System DMA 5 Package End Transfer Interrupt Enable. 0: Disable, 1: Enable. R/W 0x0 DMA5_HLAF_IRQ_EN DMA 5 Half package Transfer Interrupt Enable. 0: Disable, 1: Enable. 19 / / / 18 R/W 0x0 DMA4_QUEUE_IRQ_EN DMA 4 Queue End Transfer Interrupt Enable. 0: Disable, 1: Enable. 17 R/W 0x0 DMA4_PKG_IRQ_EN DMA 4 Package End Transfer Interrupt Enable. 0: Disable, 1: Enable. 16 R/W 0x0 DMA4_HLAF_IRQ_EN DMA 4 Half Package Transfer Interrupt Enable. 0: Disable, 1: Enable.
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System 3 / / / 2 R/W 0x0 DMA0_QUEUE_IRQ_EN DMA 0 Queue End Transfer Interrupt Enable. 0: Disable, 1: Enable. 1 R/W 0x0 DMA0_PKG_IRQ_EN DMA 0 Package End Transfer Interrupt Enable. 0: Disable, 1: Enable. 0 R/W 0x0 DMA0_HLAF_IRQ_EN DMA 0 Half Package Transfer Interrupt Enable. 0: Disable, 1: Enable 4.11.4.2.
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System 1: Enable R/W 0x0 DMA9_PKG_IRQ_EN DMA 9 Package End Transfer Interrupt Enable. 0: Disable 1: Enable 4 R/W 0x0 DMA9_HLAF_IRQ_EN DMA 9 Half package Transfer Interrupt Enable. 0: Disable 1: Enable 3 / / / 2 R/W 0x0 DMA8_QUEUE_IRQ_EN DMA 8 Queue End Transfer Interrupt Enable. 0: Disable 1: Enable 1 R/W 0x0 DMA8_PKG_IRQ_EN DMA 8 Package End Transfer Interrupt Enable. 0: Disable 1: Enable 0 R/W 0x0 DMA8_HLAF_IRQ_EN DMA 8 Half Package Transfer Interrupt Enable.
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System R/W 0x0 DMA6_HLAF_IRQ_PEND. DMA 6 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending. 23 / / / 22 R/W 0x0 DMA5_QUEUE_IRQ_PEND. DMA 5 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending. 21 R/W 0x0 DMA5_PKG_IRQ_ PEND DMA 5 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending. 20 R/W 0x0 DMA5_HLAF_IRQ_PEND. DMA 5 Half Package Transfer Interrupt Pending.
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System DMA 1 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending. R/W 0x0 DMA1_PKG_IRQ_ PEND DMA 1 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending. 4 R/W 0x0 DMA1_HLAF_IRQ_PEND. DMA 1 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect, 1: Pending. 3 / / / 2 R/W 0x0 DMA0_QUEUE_IRQ_PEND. DMA 0 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it.
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System DMA 10 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect 1: Pending R/W 0x0 DMA10_HLAF_IRQ_PEND. DMA 10 Half Package Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect 1: Pending 7 / / / 6 R/W 0x0 DMA9_QUEUE_IRQ_PEND. DMA 9 Queue End Transfer Interrupt Pending. Set 1 to the bit will clear it. 0: No effect 1: Pending 5 R/W 0x0 DMA9_PKG_IRQ_ PEND DMA 9 Package End Transfer Interrupt Pending. Set 1 to the bit will clear it.
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System R/W 0x0 DMA10_SEC DMA channel 10 security. 0: Secure, 1: Non-secure. 9 R/W 0x0 DMA9_SEC DMA channel 9 security. 0: Secure, 1: Non-secure. 8 R/W 0x0 DMA8_SEC DMA channel 8 security. 0: Secure, 1: Non-secure. 7 R/W 0x0 DMA7_SEC DMA channel 7 security. 0: Secure, 1: Non-secure. 6 R/W 0x0 DMA6_SEC DMA channel 6 security. 0: Secure, 1: Non-secure. 5 R/W 0x0 4 R/W 0x0 3 R/W 2 nt ia l 10 id e 1: Non-secure. nf DMA5_SEC DMA channel 5 security. 0: Secure, 1: Non-secure.
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System 4.11.4.6. DMA Auto Gating Register (Default Value: 0x00000000) Offset:0x28 Register Name: DMA_AUTO_GATE_REG R/W Default/Hex Description 31:3 / / / 2 R/W 0x0 DMA_MCLK_CIRCUIT. DMA MCLK interface circuit auto gating bit. 0: Auto gating enable 1: Auto gating disable. 1 R/W 0x0 DMA_COMMON_CIRCUIT. DMA common circuit auto gating bit. 0: Auto gating enable 1: Auto gating disable. 0 R/W 0x0 DMA_CHAN_CIRCUIT. DMA channel circuit auto gating bit.
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System RO 0x0 DMA7_STATUS DMA Channel 7 Status. 0: Idle 1: Busy 6 RO 0x0 DMA6_STATUS DMA Channel 6 Status. 0: Idle 1: Busy 5 RO 0x0 DMA5_STATUS DMA Channel 5 Status. 0: Idle 1: Busy 4 RO 0x0 DMA4_STATUS DMA Channel 4 Status. 0: Idle 1: Busy. 3 RO 0x0 DMA3_STATUS DMA Channel 3 Status. 0: Idle 1: Busy. 2 RO 0x0 DMA2_STATUS DMA Channel 2 Status. 0: Idle, 1: Busy. 1 RO 0x0 0 RO id e nt ia l 7 co nf DMA1_STATUS DMA Channel 1 Status. 0: Idle, 1: Busy.
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System 4.11.4.9. DMA Channel Pause Register (Default Value: 0x00000000) Offset: 0x100+N*0x40+0x4(N=0~11) Register Name: DMA_PAU_REG Bit R/W Default/Hex Description 31:1 / / / 0 R/W 0x0 DMA_PAUSE. Pausing DMA Channel Transfer Data. 0: Resume Transferring, 1: Pause Transferring. 4.11.4.10. DMA Channel Descriptor Address Register (Default Value: 0x00000000) Register Name: DMA_DESC_ADDR_REG Bit R/W Default/Hex Description 31:0 R/W 0x0 DMA_DESC_ADDR DMA Channel Descriptor Address.
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System / / / 10:9 RO 0x0 DMA_SRC_DATA_WIDTH. DMA Source Data Width. 00: 8-bit 01: 16-bit 10: 32-bit 11: 64-bit 8 / / / 7:6 RO 0x0 DMA_SRC_BST_LEN. DMA Source Burst Length. 00: 1 01: 4 10: 8 11: 16 5 RO 0x0 DMA_SRC_ADDR_MODE. DMA Source Address Mode 0: Linear Mode 1: IO Mode 4:0 RO 0x0 DMA_SRC_DRQ_TYPE. DMA Source DRQ Type The details in DRQ Type and Port Corresponding Relation. id e nt ia l 15:11 DMA Channel Current Source Address Register (Default Value: 0x00000000) nf 4.11.4.
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System DMA Channel Byte Counter Left, read only. 4.11.4.15. DMA Channel Parameter Register (Default Value: 0x00000000) Offset: 0x100+N*0x40+0x1C(N=0~11) Register Name: DMA_PARA_REG Bit R/W Default/Hex Description 31:8 / / / 7:0 RO 0x0 WAIT_CYC. Wait Clock Cycles n. 4.11.4.16. DMA Former Descriptor Address Register (Default Value: 0x00000000) Register Name: DMA_FDESC_ADDR_REG Bit R/W Default/Hex Description 31:0 RO 0x0 DMA_FDESC_ADDR.
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System 4.12. GIC 4.12.1.
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System / / 37 / / 38 TWI 0 TWI 0 interrupt 39 TWI 1 TWI 1 interrupt 40 TWI 2 TWI 2 interrupt 41 / / 42 / / 43 PA_EINT PA interrupt 44 OWA OWA interrupt 45 I2S/PCM-0 I2S/PCM-0 interrupt 46 I2S/PCM-1 I2S/PCM-1 interrupt 47 I2S/PCM-2 I2S/PCM-2 interrupt 48 / / 49 PG_EINT PG_EINT interrupt 50 Timer 0 Timer 0 interrupt 51 Timer 1 Timer 1 interrupt 52 / / 53 / / 54 / 55 / 56 / 57 Watchdog 58 / 59 / 60 / 61 Audio Codec Audio Codec interrupt 62
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System / / 81 M-box M-box interrupt 82 DMA DMA channel interrupt 83 HS Timer HS Timer interrupt 84 / / 85 / / 86 / / 87 / / 88 SMC SMC interrupt 89 / / 90 VE VE interrupt 91 / / 92 SD/MMC 0 SD/MMC Host Controller 0 interrupt 93 SD/MMC 1 SD/MMC Host Controller 1 interrupt 94 SD/MMC 2 SD/MMC Host Controller 2 interrupt 95 / / 96 / / 97 SPI 0 SPI 0 interrupt 98 SPI 1 99 / 100 / 101 / 102 NAND 103 USB-OTG_Device 104 USB-OTG_EHCI0 105 USB-OTG_OH
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System TVE TVE interrupt 125 DIT DIT interrupt 126 SS_NS SS_NS interrupt 127 DE DE interrupt 128 / / 129 GPU-GP GPU-GP interrupt 130 GPU-GPMMU GPU-GPMMU interrupt 131 GPU-PP0 GPU-PP0 interrupt 132 GPU-PPMMU0 GPU-PPMMU0 interrupt 133 GPU-PMU GPU-PMU interrupt 134 GPU-PP1 GPU-PP1 interrupt 135 GPU-PPMMU1 GPU-PPMMU1 interrupt 136 / / 137 / / 138 / / 139 / / 140 CTI0 CTI0 interrupt 141 CTI1 CTI1 interrupt 142 CTI2 143 CTI3 144 COMMTX0 145 COMMTX1 146
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System 4.13. Message Box 4.13.1. Overview Message Box provides an MSGBox-interrupt mechanism for on-chip processors intercommunication. The MSGBox-interrupt mechanism allows the software to establish a communication channel between the two users through a set of registers and associated interrupt signals by sending or receiving messages.
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System 4.13.2.1. Typical Applications Typical Application Flow Chart START Set a MSG Queue as a Transmitter or a receiver? As a receiver ia l As a transmitter Enable the RECEPTION IRQ id e nt N A new message has received? nf Check the MSG status or FIFO status if it is not full? Y N Read the MSG REG to fetch the message co Y Write a message to the MSG REG IF the Message Queue FIFO is empty? N Y Clear the Reception IRQ Pending FINISH FINISH Figure 4-7.
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System 4.13.2.2. Functional Block Diagram MSGBox MSGBOX_CTRL_REG0 MSGBOX_CTRL_REG1 For user0 MSGBOX_IRQ_EN_REG_0 MSGBOX_IRQ_STATUS_REG_0 For user1 MSGBOX_IRQ_EN_REG_1 MSGBOX_IRQ_STATUS_REG_1 USER1 ia l USER0 nt MSGBox Message Queue m (m : from 0 to 7) MSGBOX_FIFO_STATUS_REG_M id e MSGBOX_MSG_STATUS_REG_M Four Message FIFO nf MSGBOX_MSG_REG_M co Figure 4-8. Message Box Functional Block Diagram 4.13.3. Operation Principle 4.13.3.1.
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System • Set a Message Queue as a transmitter (in the MSGBOX_CTRL_REG0/1). • Check the FIFO status or the message status (in the MSGBOX_FIFO_STATUS_REG_M or MSGBOX_MSG_ STATUS_ REG_M). • Write the message to the corresponding MSGBOX_MSG_REG_M register, if space is available. The transmit interrupt might be used when the initial MSGBox status indicates that the Message Queue is full. In this case, the sender can enable the corresponding MSGBOX_IRQ_EN_REG_U interrupt for the user.
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System 4.13.5. Message Box Register Description 4.13.5.1. MSGBox Control Register 0(Default Value: 0x10101010) Offset: 0x00 Register Name: MSGBOX_CTRL_REG0 R/W Default/Hex Description 31:29 / / / 28 R/W 0x1 TRANSMIT_MQ3. Message Queue 3 is a Transmitter of user u. 0: user0 1: user1 27:25 / / / 24 R/W 0x0 RECEPTION_MQ3. Message Queue 3 is a Receiver of user u. 0: user0 1: user1 23:21 / / / 20 R/W 0x1 TRANSMIT_MQ2. Message Queue 2 is a Transmitter of user u.
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System 0: user0 1: user1 4.13.5.2. MSGBox Control Register 1(Default Value: 0x10101010) Offset: 0x04 Register Name: MSGBOX_CTRL_REG1 R/W Default/Hex Description 31:29 / / / 28 R/W 0x1 TRANSMIT_MQ7. Message Queue 7 is a Transmitter of user u. 0: user0 1: user1 27:25 / / / 24 R/W 0x0 RECEPTION_MQ7. Message Queue 7 is a Receiver of user u. 0: user0 1: user1 23:21 / / / 20 R/W 0x1 TRANSMIT_MQ6. Message Queue 6 is a Transmitter of user u.
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System 0 R/W 0x0 RECEPTION_MQ4. Message Queue 4 is a Receiver of user u. 0: user0 1: user1 4.13.5.3. MSGBox IRQ Enable Register (Default Value: 0x00000000) Register Name: MSGBOXU_IRQ_EN_REG Bit R/W Default/Hex Description 31:16 / / / 15 R/W 0x0 TRANSMIT_MQ7_IRQ_EN. 0: Disable 1: Enable (It will notify user u by interrupt when Message Queue 7 is not full.) 14 R/W 0x0 RECEPTION_MQ7_IRQ_EN.
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System 1: Enable (It will notify user u by interrupt when Message Queue 3 is not full.) 6 R/W 0x0 RECEPTION_MQ3_IRQ_EN. 0: Disable 1: Enable (It will notify user u by interrupt when Message Queue 3 has received a new message.) 5 R/W 0x0 TRANSMIT_MQ2_IRQ_EN. 0: Disable 1: Enable (It will notify user u by interrupt when Message Queue 2 is not full.) 4 R/W 0x0 RECEPTION_MQ2_IRQ_EN. 0: Disable 1: Enable (It will notify user u by interrupt when received a new message.
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System R/W 0x1 TRANSMIT_MQ6_IRQ_PEND. 0: No effect, 1: Pending. This bit will be pending for user u when Message Queue 6 is not full. Set one to this bit will clear it. 12 R/W 0x0 RECEPTION_MQ6_IRQ_PEND. 0: No effect, 1: Pending. This bit will be pending for user u when Message Queue 6 has received a new message. Set one to this bit will clear it. 11 R/W 0x1 TRANSMIT_MQ5_IRQ_PEND. 0: No effect, 1: Pending. This bit will be pending for user u when Message Queue 5 is not full.
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System 0: No effect, 1: Pending. This bit will be pending for user u when Message Queue 1 has received a new message. Set one to this bit will clear it. 1 R/W 01 TRANSMIT_MQ0_IRQ_PEND. 0: No effect, 1: Pending. This bit will be pending for user u when Message Queue 0 is not full. Set one to this bit will clear it. 0 R/W 0x0 RECEPTION_MQ0_IRQ_PEND. 0: No effect, 1: Pending. This bit will be pending for user u when Message Queue 0 has received a new message. Set one to this bit will clear it. ia l 4.
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System R/W 0x0 The message register stores the next to be read message of the message FIFO queue. Reads remove the message from the FIFO queue. co nf id e nt ia l 31:0 H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System 4.14. Spinlock 4.14.1. Overview Spinlock provides hardware assistance for synchronizing the processes running on multiple processors in the device. The SpinLock module implements thirty-two 32-bit spinlocks (or hardware semaphores), which provide an efficient way to perform a lock operation of a device resource using a single read access, thus avoiding the need for a ‘read-modify-write’ bus transfer that not all the programmable cores are capable of.
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System 4.14.2. Functionalities Description 4.14.2.1. Typical Applications Start N Take a Lock Is the Lock Taken? (SPINLOCK_LOCK_REG_i[0]=0?) Y Take the Lock ia l Critical code section Free a Lock nt SPINLOCK_LOCK_REG_i[0]=0 id e Free the Lock End co nf Figure3-11. Spinlock Typical Application Flow Chart 4.14.2.2. Functional Block Diagram Write 0/1 Read: 1 Write 0 Unlocked State (TAKEN_bit=0) Locked State (TAKEN_bit=1) Read: 0 Write 1 Reset Figure 4-9.
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System 4.14.3. Operation Principle 4.14.3.1. Spinlock clock gating and software reset Spinlock clock gating should be open before using it. Setting Bus Clock Gating Register1 bit[22] to 1 could activate Spinlock and then de-asserting it's software reset. Setting AHB1 Module Software Reset Register bit[22] to 1 could de-assert the software reset of Spinlock. If it is no need to use spinlock, both the gating bit and software reset bit should be set 0. ia l 4.14.3.2.
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System R/W Default/Hex Description 31:30 / / / 29:28 RO 0x1 LOCKS_NUM. Number of lock registers implemented. 0x1: This instance has 32 lock registers. 0x2: This instance has 64 lock registers. 0x3: This instance has 128 lock registers. 0x4: This instance has 256 lock registers. 27:16 / / / 15:9 / / / 8 RO 0x0 IU0. In-Use flag0, covering lock register0-31. 0: All lock register 0-31 are in the Not Taken state. 1: At least one of the lock register 0-31 is in the Taken state.
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System 4.14.6.
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System 4.15. Crypto Engine 4.15.1. Overview The Crypto Engine is one encrypt/ decrypt function accelerator. It is suitable for a variety of applications. It can support encryption ,decryption and calculate the hash value. Several modes are supported by the Crypto Engine. The Crypto Engine has a special internal DMA(IDMA) controller to transfer data .
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System 4.15.2.1. Block Diagram NS Interrupt S Interrupt SHA512 HMAC CBC - MAC PRNG AHB SHA 384 TRNG Register SHA 256 SHA 224 Task management DES / 3DES SHA1 AES ia l MD5 Efuse keys RXFIFO nt Symmeric/Hash co nf TXFIFO id e MBUS Figure 4-10. Crypto Engine Block Diagram 4.15.2.2. Crypto Engine Task Descriptor Crypto Engine task deccriptor is 44*4 Byte memory. H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System task1 task chaining id=0 common ctl symmetric ctl reserved key descriptor iv descriptor ctr descriptor data len src adr0 src len0 ………… taskn task chaining id=0 common ctl symmetric ctl reserved key descriptor iv descriptor ctr descriptor data len src adr0 src len0 … src adr7 src len7 dst adr0 dst len0 dst adr7 dst len7 next descriptor(task1) reserved[3] dst adr7 dst len7 next descriptor(task2) reserved[3] dst adr7 dst len7 next descriptor(taskn) reserved[3] … src adr7 src len7 dst adr0 dst
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System task_descriptor_queue symmetric control(32bit) ia l CE_Method 0: AES 1: DES 2: Triple DES (3DES) 3~15: reserved 16: MD5 17: SHA-1 18: SHA-224 19: SHA-256 20: SHA384 21: SHA512 22: HMAC-SHA1 23~47: reserved 48: TRNG 49: PRNG 50~64: reserved nt 6:0 Description 31:24 / 23:20 SKEY_Select key select for AES 0: Select input CE_KEYx (Normal Mode) 1: Select {SSK} 2: Select {HUK} 3: Select {RSSK} 4-7: Reserved 8-15: Select internal Key n (n from 0 to 7) 19:18 CFB_Mode_Width 0:1-bits 1:8-bits 2:64-
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System 4: Output feedback (OFB)mode 5: Cipher feedback (CFB)mode 6: CBC-MAC mode Other: reserved / 3:2 CTR_Width Counter Width for CTR Mode 0: 16-bits Counter 1: 32-bits Counter 2: 64-bits Counter 3: 128-bits Counter 1:0 AES_Key_Size 0: 128-bits 1: 192-bits 2: 256-bits 3: Reserved 4.15.3.
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System Bit R/W Default/Hex Description 31:0 R/W 0 Task_Descriptor_Queue_Address 4.15.4.2.
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System 31:1 0 / R/W / / 0 Task_Load When set , CE starts to load the configure of task from task descriptor queue and start to perform the task. 4.15.4.6. Crypto Engine Error Status Register(Default Value: 0x00000000) Offset: 0x18 Register Name: CE_ESR R/W Default/Hex Description 31:4 / / / 3 / / / 0 AES_Access_Keysram_Status 0: AES could perform request if destination address is keysram. 1: AES couldn't perform request if destination address is not keysram.
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System 4.15.4.9. Crypto Engine Current Source Address Register(Default Value: 0x00000000) Offset: 0x24 Register Name: CE_CSAR Bit R/W Default/Hex Description 31:0 R 0 Current source address of the executing task 4.15.4.10.
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System address increasing direction address A+1 High-order byte Big-endian Low-order byte LSB nf MSB address A id e little-endian nt ia l (6) Secure CPU and non-secure CPU support separately one task channel, every task channel has an interrupt enable bit and an interrupt status bit.
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nt co nf id e 0x30,0x70,0xdd,0x17,0xf7,0x0e,0x59,0x39, 0xff,0xc0,0x0b,0x31,0x68,0x58,0x15,0x11, 0x64,0xf9,0x8f,0xa7,0xbe,0xfa,0x4f,0xa4}; For SHA256: unsigned char iv_sha256[32]={ 0x6a,0x09,0xe6,0x67,0xbb,0x67,0xae,0x85, 0x3c,0x6e,0xf3,0x72,0xa5,0x4f,0xf5,0x3a, 0x51,0x0e,0x52,0x7f,0x9b,0x05,0x68,0x8c, 0x1f,0x83,0xd9,0xab,0x5b,0xe0,0xcd,0x19}; For SHA384: unsigned char iv_sha384[64]={ 0xcb,0xbb,0x9d,0x5d,0xc1,0x05,0x9e,0xd8, 0x62,0x9a,0x29,0x2a,0x36,0x7c,0xD5,0x07, 0x91,0x59,0x01,0x5a,0x30,0x70,0xdd,0x17
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System 4.16. Security ID 4.16.1. Overview There is one 2Kbit on chip EFUSE, which provides 128-bit, 64-bit and one 32-bit electrical fuses for security application. The users can use them as root key, security JTAG key and other applications. It includes the following features: nf id e nt ia l 128-bit electrical fuses for chip ID 64-bit electrical fuses for thermal sensor co   H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System 4.17. Secure Memory Controller 4.17.1. Overview The SMC is an Advanced Microcontroller Bus Architecture compliant System-on-Chip peripheral. It is a high-performance, area-optimized address space controller with on-chip AMBA bus interfaces that conform to the AMBA Advanced extensible Interface protocol and the AMBA Advanced Peripheral Bus protocol. You can configure the SMC to provide the optimum security address region control functions required for your intended application. id e 4.17.2.
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System 4.17.2.1. DRM Block Diagram G. NS.M stands for General Non-secure Master D. NS.M stands for Non-secure Master appointed by DRM S.M. stands for Secure Mater Non-secure Zone G.NS.M only can read data from NSZ and write data into NSZ DRM D.NS.M can read data from NSZ and DRM, but only can write data into DRM Secure Zone S.M can read data from the whole DRAM SPACE DRAM SPACE G.NS.M NSZ SZ D.NS.M NSZ S.M SZ id e SZ DRM ia l NSZ DRM nt DRM 4.17.2.2. Master ID Table nf Figure 4-12.
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System 4.17.2.3. Region Size Table Table 4-3.
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System 4.17.2.5.
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System SMC_MST_ATTRI_REG 0x48 SMC Master Attribute Register DRM_MASTER_EN_REG 0x50 DRM Master Enable Register DRM_ILLACCE_REG 0x58 DRM Illegal Access Register DRM_STATADDR_REG 0x60 DRM Start Address Register DRM_ENDADDR_REG 0x68 DRM End Address Register SMC_REGION_SETUP_LO_REG 0x100+N*0x10 Region Setup Low Register N (N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15) SMC_REGION_SETUP_HI_REG 0x104+N*0x10 Region Setup High Register N (N=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15) SMC_REGION_ATTR_REG 0
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System 2’b00 = sets smc_int LOW and issues an OKEY response 2’b01 = sets smc_int LOW and issues a DECERR response 2’b10 = sets smc_int HIGH and issues an OKEY response 2’b11 = sets smc_int HIGH and issues a DECERR response Note:This action is only valid for CPU access, not for MBUS and DMA access. 4.17.4.3. SMC Lockdown Range Register(Default Value: 0x00000000) Offset: 0x8 Register Name: SMC_LD_RANGE_REG R/W Default/Hex Description 31 R/W 0x0 LOCKDOWN_EN.
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System 4.17.4.5. SMC Interrupt Status Register(Default Value: 0x00000000) Offset: 0x10 Register Name: SMC_INT_STATUS_REG Bit R/W Default/Hex Description 31:2 / / / 1 R 0x0 INT_OVERRUN. When set to 1, it indicates the occurrence of two or more region permission failure since the interrupt was last cleared. 0 R 0x0 INT_STATUS. Return the status of the interrupt. 0: interrupt is inactive. 1: interrupt is active. Offset: 0x14 ia l 4.17.4.6.
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System 31:0 R/W 0x0 SMC_MASTER_SEC. SMC Master n Secure Configuration.(n = 0~31，see the Table 4-2 for detail) 0: secure 1: non-secure. 4.17.4.9. SMC Fail Address Register(Default Value: 0x00000000) Offset: 0x20 Register Name: SMC_FAIL_ADDR_REG R/W Default/Hex Description 31:0 R 0x0 FIRST_ACCESS_FAIL. Return the address bits [31:0] of the first access to fail a region permission check after the interrupt was cleared. For external 16-bit DDR2, the address [2:0] is fixed to zero.
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System 4.17.4.11. SMC Fail ID Register(Default Value: 0x00001F00) Offset: 0x2C Register Name: SMC_FAIL_ID_REG R/W Default/Hex Description 31:24 / / / 23:16 R 0x0 FAIL_BST_LEN. Fail burst length. 0 = 1 word length …… 0xf =16 words length 15:8 / / / 7:0 R 0x0 FAIL_MASTER_ID. Fail Master ID. The value stands for master id, see the Table 4-2 MASTER and MASTER ID for detail.
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System 4.17.4.14. SMC Master Attribute Register(Default Value: 0x00000000) Offset: 0x48 Register Name: SMC_MST_ATTRI_REG Bit R/W Default/Hex Description 31:0 R/W 0x0 MST_ATTRI. 0: The secure attribute of master is up to master security extensions; 1: The secure attribute of master is up to Master Secure Register. DRM Master Enable Register(Default Value: 0x00000000) Offset: 0x50 Register Name: DRM_MASTER_EN_REG R/W Default/Hex Description 31 R/W 0x0 DRM_EN. DRM enable.
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System 4.17.4.17. DRM Start Address Register(Default Value: 0x00000000) Offset: 0x60 Register Name: DRM_STATADDR_REG Bit R/W Default/Hex Description 31:15 R/W 0x0 DRM_STATADDR_REG. 14:0 / / / 4.17.4.18. DRM End Address Register(Default Value: 0x00000000) Offset: 0x68 Register Name: DRM_ENDADDR_REG R/W Default/Hex Description 31:15 R/W 0x0 DRM_ENDADDR_REG. 14:0 / / / SMC Region Setup Low Register(Default Value: 0x00000000) nt 4.17.4.19.
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System region size. If you program a region size to be 8GB or more, then the SMC might ignore certain bits depending on the region size. 4.17.4.21. SMC Region Attributes Register(Default Value: 0x00000000) Register Name: SMC_REGION_ATTR_REG Bit R/W Default/Hex Description 31:28 R/W 0x0 REGION_ATTR_SPN. SP. Permission setting for region . if an AXI transaction occurs to region n, the value in the sp field controls whether the SMC permits the transaction to proceed. .
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System 4.18. Secure Memory Touch Arbiter 4.18.1. Overview Secure Memory Touch Arbiter provides a software interface to the protection bits in a secure system in a TrustZone design. It provides system flexibility that enables to configure different areas of memory as secure or non-secure. The SMTA includes the following features:  It has protection bits to enable you to program some areas of memory as secure or non–secure. ia l 4.18.2. Functionalities Description nt 4.18.2.1.
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System 4.18.3.
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System Configuration Table4-6 in detail). 4.18.4.3. SMTA DECPORT0 Clear Register(Default Value: 0x00000000) Offset: 0xC Register Name: SMTA_DECPORT0_CLR_REG R/W Default/Hex Description 31:8 / / / 7:0 WO 0x0 CLR_DEC_PROT0_OUT. Clears the corresponding decode protection output: 0: = No effect 1: = Set decode region to secure. There is one bit of the register for each protection output (See the SMTA Configuration Table4-6 in detail). ia l Bit Offset: 0x10 nt 4.18.4.4.
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System 4.18.4.6. SMTA DECPORT1 Clear Register(Default Value: 0x00000000) Offset: 0x18 Register Name: SMTA_DECPORT1_CLR_REG Bit R/W Default/Hex Description 31:8 / / / 7:0 WO 0x0 CLR_DEC_PROT1_OUT. Clears the corresponding decode protection output: 0: = No effect 1: = Set decode region to secure. There is one bit of the register for each protection output (See the SMTA Configuration Table4-6 in detail). Offset: 0x1C ia l 4.18.4.7.
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System / / / 7:0 WO 0x0 CLR_DEC_PROT2_OUT. Clears the corresponding decode protection output: 0: = No effect 1: = Set decode region to secure. There is one bit of the register for each protection output (See the SMTA Configuration Table4-6 in detail). co nf id e nt ia l 31:8 H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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System 4.19. Thermal Sensor Controller 4.19.1. Overview The thermal sensors have become common elements in wide range of modern system on chip (SOC) platform. Thermal sensors are used to constantly monitor the temperature on the chip. H3 embeds one thermal sensor located in the CPU .The thermal sensor Generates interrupt to SW to lower temperature via DVFS, on reaching a certain thermal threshold.
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System 0x01C25000 Register Name Offset Description THS_CTRL0 0x00 THS Control Register0 THS_CTRL1 0x04 THS Control Register1 ADC_CDAT 0x14 ADC calibration data Register THS_CTRL2 0x40 THS Control Register2 THS_INT_CTRL 0x44 THS Interrupt Control Register THS_STAT 0x48 THS Status Register THS_ALARM_CTRL 0x50 Alarm threshold Control Register THS_SHUTDOWN_CTRL 0x60 Shutdown threshold Control Register THS_FILTER 0x70 Median filter Control Register THS_CDATA 0X74 Thermal Sensor C
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System 4.19.4.3. ADC calibration Data Register (Default Value: 0x00000000) Offset: 0x14 Register Name: ADC_CDAT_REG Bit R/W Default/Hex Description 31:12 / / / 11:0 R/W 0xxxx ADC_CDAT. ADC calibration data 4.19.4.4. THS Control Register2 (Default Value: 0x00040000) Offset: 0x40 Register Name: THS_CTRL_REG2 R/W Description 31:16 R/W 0x4 SENSOR_ACQ1. Sensor acquire time CLK_IN/(N+1) 15:3 / / / 2 1 / / / / / / 0 R/W 0x0 SENSE_EN.
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System 0: No select 1: Select 3 / / / 2 1 / / / / / / 0 R/W 0x0 ALARM_INT_EN. Selects Alert interrupt for sensor 0: No select 1: Select 4.19.4.6. THS status Register (Default Value: 0x00000000) Offset: 0x48 Register Name: THS_STAT_REG R/W Default/Hex Description 31:15 / / / 14 / / / 13 / / / 12 R/W 0x0 ALARM_ OFF_STS.
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System 4.19.4.7. Alarm threshold Control Register (Default Value: 0x05a00684) Offset: 0x50 Register Name: THS0_ALARM_CTRL_REG Bit R/W Default/Hex Description 31:28 / / / 27:16 R/W 0x5A0 ALARM0_T_HOT. Thermal sensor0 Alarm Threshold for hot temperature 15:12 / / / 11:0 R/W 0x684 ALARM0_T_HYST Thermal sensor0 Alarm threshold for hysteresis temperature 4.19.4.8.
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System 31:28 / / / 27:16 / / / 15:12 / / / 11:0 R/W 0x800 THS_CDATA. Thermal Sensor calibration data 4.19.4.11. THS Data Register (Default Value: 0x00000000) Offset: 0x80 Register Name: THS_DATA _REG R/W Default/Hex Description 31:12 / / / 11:0 R 0x0 THS_DATA. Temperature measurement data of sensor ia l Bit nt 4.19.5.
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System 4.20. KEY_ADC 4.20.1. Overview KEY_ADC is 6-bit resolution ADC for key application. The KEY_ADC can work up to 250Hz conversion rate. nt ia l The KEY_ADC includes the following features:  Supports APB 32-bits bus width,reference voltage is 2.0V  Support interrupt  Support Hold Key and General Key  Support Single Key and Continue Key mode  Support 6-bits resolution  Voltage input range between 0V to 2.0V  Sample rate up to 250Hz id e 4.20.2.
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System second interrupt, it will send hold key interrupt to the host; If the control Logic get the first interrupt, In a certain time range (program can set), get second interrupt, it will send key down interrupt to the host; If the control logic only get the second interrupt, doesn’t get the first interrupt, it will send already hold interrupt to the host. The KEY_ADC have three mode, Normal Mode、Single Mode and Continue Mode.
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System 10: Continue Mode R/W 0x1 LEVELA_B_CNT. Level A to Level B time threshold select, judge ADC convert value in level A to level B in n+1 samples 7 R/W 0X0 KEY_ADC_HOLD_KEY_EN KEY_ADC Hold Key Enable 0: Disable 1: Enable 6 R/W 0x1 KEY_ADC_HOLD_EN. KEY_ADC Sample hold Enable 0: Disable 1: Enable 5: 4 R/W 0x2 LEVELB_VOL. Level B Corresponding Data Value setting (the real voltage value) 00: 0x3C (~1.9v) 01: 0x39 (~1.8v) 10: 0x36 (~1.7v) 11: 0x33 (~1.6v) 3: 2 R/W 0x2 KEY_ADC_SAMPLE_RATE.
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System ADC Hold Key IRQ Enable 0: Disable 1: Enable 1 0 R/W R/W 0x0 ADC_KEYDOWN_EN ADC Key Down Enable 0: Disable 1: Enable 0x0 ADC_DATA_IRQ_EN. ADC Data IRQ Enable 0: Disable 1: Enable Offset: 0x08 ia l 4.20.4.3. KEY_ADC Interrupt Status Register (Default Value: 0x00000000) Register Name:KEY_ADC_INTS_REG R/W Default/Hex Description 31:5 / / / 4 R/W 0x0 ADC_KEYUP_PENDING. ADC Key up pending Bit When general key pull up, it the corresponding interrupt is enabled.
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System 0: No IRQ 1: IRQ Pending Notes: Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable. 0 R/W 0x0 ADC_DATA_PENDING. ADC Data IRQ Pending Bit 0: No IRQ 1: IRQ Pending Notes: Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable. 4.20.4.4. KEY_ADC Data Register (Default Value: 0x00000000) Register Name: KEY_ADC_DATA_REG R/W Default/Hex Description 31:6 / / / 5:0 R 0x0 KEY_ADC_DATA.
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System 4.21. Audio Codec 4.21.1. Overview The embedded Audio Codec is a high-quality stereo audio codec designed for embed device. It provides a stereo DAC for playback, and a stereo ADC for recording.
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System 4.21.2.2. Filter/Reference MBIAS O Bias voltage output for main microphone VRA1 O internal reference voltage VRA2 O internal reference voltage VRP O internal reference voltage AVCC P Analog power AGND G Analog ground 4.21.3. Data Path Diagram + MIC1N MIC2P M M M M M + G ADC_L M M M M M + G ADC_R G + MIC2N G - G LINEINR G nf LINEINL M M co M LINEOUTL LINEOUTR -1 G M G M 2.5V id e MIC1P MICBIASEN nt MICBIAS ia l 4.21.2.3.
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System 0x008 DAC FIFO Status Register AC_ADC_FIFOC 0x010 ADC FIFO Control Register AC_ADC_FIFOS 0x014 ADC FIFO Status Register AC_ADC_RXDATA 0x018 ADC RX Data Register AC_DAC_TXDATA 0x020 DAC TX Data Register AC_DAC_CNT 0x040 DAC TX FIFO Counter Register AC_ADC_CNT 0x044 ADC RX FIFO Counter Register AC_DAC_DG 0x048 DAC Debug Register AC_ADC_DG 0x04C ADC Debug Register AC_DAC_DAP_CTR 0X060 DAC DAP Control Register AC_ADC_DAP_CTR 0x070 ADC DAP Control Register AC_ADC_DAP_LCTR
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System 0x144 DAC DRC Compressor Slope High Setting Register AC_DAC_DRC_LKC 0x148 DAC DRC Compressor Slope Low Setting Register 0x14C DAC DRC Compressor High Output at Compressor Threshold Register AC_DAC_DRC_LOPC 0x150 DAC DRC Compressor Low Output at Compressor Threshold Register AC_DAC_DRC_HLT 0x154 DAC DRC Limiter Theshold High Setting Register AC_DAC_DRC_LLT 0x158 DAC DRC Limiter Theshold Low Setting Register AC_DAC_DRC_HKl 0x15C DAC DRC Limiter Slope High Setting Register AC_DAC_DRC_
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System 0x224 ADC DRC Right Peak filter High Release Time Coef Register AC_ADC_DRC_RPFLRT 0x228 ADC DRC Right Peak filter Low Release Time Coef Register AC_ADC_DRC_LRMSHAT 0x22C ADC DRC Left RMS Filter High Coef Register AC_ADC_DRC_LRMSLAT 0x230 ADC DRC Left RMS Filter Low Coef Register AC_ADC_DRC_RRMSHAT 0x234 ADC DRC Right RMS Filter High Coef Register AC_ADC_DRC_RRMSLAT 0x238 ADC DRC Right RMS Filter Low Coef Register AC_ADC_DRC_HCT 0x23C ADC DRC Compressor Theshold High Setting Registe
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System AC_PR_CFG AC Parameter Configuration Register (0X01F015C0) 0X00 LINEOUT PA Gating Control Register LOMIXSC 0X01 Left Output Mixer Source Select Control Register ROMIXSC 0X02 Right Output Mixer Source Select Control Register DAC_PA_SCR 0X03 DAC Analog Enable And PA Source Control Register LINEIN_GCTR 0X05 Linein Gain Control Register MIC_GCTR 0X06 MIC1 And MIC2 Gain Control Register PAEN_CTR 0X07 PA Enable And LINEOUT Control Register LINEOUT_VOLC 0X09 LINEOUT Volume Control R
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System High Pass Filter Enable 0: Disable 1: Enable 17:12 R/W 0x0 DVOL Digital volume control: DVC, ATT=DVC[5:0]*(-1.16Db) 64 steps, -1.16Db/step 11:1 / / / 0 R/W 0x0 HUB_EN Audio Hub Enable 0: Disable 1: Enable Offset: 0x04 ia l 4.21.5.2. 0x04 DAC FIFO Control Register(Default Value: 0x00000F00) Register Name: AC_DAC_FIFOC R/W Default/Hex Description 31:29 R/W 0X0 DAC_FS Sample Rate Of DAC 000: 48KHz 010: 24KHz 100: 12KHz 110: 192KHz 001: 32KHz 011: 16KHz 101: 8KHz 111: 96KHz 44.
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System When TX FIFO Available Room Less Than Or Equal N, DRQ Request Will Be De-Asserted. N Is Defined Here: 00: IRQ/DRQ De-Asserted When WLEVEL > TXTL 01: 4 10: 8 11: 16 / / / 14:8 R/W 0XF TX_TRIG_LEVEL TX FIFO Empty Trigger Level (TXTL[12:0]) Interrupt and DMA request trigger level for TX FIFO normal condition. IRQ/DRQ Generated when WLEVEL ≤ TXTL Notes: 1. WLEVEL represents the number of valid samples in the TX FIFO 2.
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System Write ‘1’ To Flush TX FIFO, Self Clear to ‘0’ 4.21.5.3.
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System 011: 16KHz 101: 8KHz 111: Reserved 44.1KHz/22.05KHz/11.
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System 1: 24 bits / / / 4 R/W 0X0 ADC_DRQ_EN ADC FIFO Data Available DRQ Enable 0: Disable 1: Enable 3 R/W 0X0 ADC_IRQ_EN ADC FIFO Data Available IRQ Enable 0: Disable 1: Enable 2 / / 1 R/W 0X0 ADC_OVERRUN_IRQ_EN ADC FIFO Over Run IRQ Enable 0: Disable 1: Enable 0 R/W 0X0 ADC_FIFO_FLUSH ADC FIFO Flush Write ‘1’ to flush TX FIFO, self clear to ‘0’ nt ia l 5 Offset: 0x14 id e 4.21.5.5.
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System 0 / / / 4.21.5.6. 0x18 ADC RX DATA Register(Default Value: 0x00000000) Offset: 0x18 Register Name: AC_ADC_RXDATA Bit R/W Default/Hex Description 31:0 R 0X0 RX_DATA RX Sample Host can get one sample by reading this register. The left channel sample data is first and then the right channel sample. Offset: 0x20 ia l 4.21.5.7.
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System The audio sample number of writing into RXFIFO. When one sample is written by Digital Audio Engine, the RX sample counter register increases by one. The RX sample counter register can be set to any initial valve at any time. After been updated by the initial value, the counter register should count on base of this initial value Notes: It is used for Audio/ Video Synchronization 4.21.5.10.
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System / 4.21.5.12. / / 0x60 DAC DAP Control Register(Default Value: 0x00000000) Offset: 0x60 Register Name: AC_DAC_DAP_CTR R/W Default/Hex Description 31 R/W 0X0 DDAP _EN DAP for dac Enable 0 : bypass 1 : enable 30:16 / / / 15 R/W 0X0 DAC_DRC_EN DRC enable control 0:disable 1:enable 14 R/W 0X0 DAC_DRC_HPF_EN HPF enable control 0:disable 1:enable 13:0 / / / id e 0x70 ADC DAP Control Register(Default Value: 0x00000000) nf 4.21.5.13.
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System Left channel AGC saturation flag 0 : no saturation 1: saturation R 0x0 ADAP_LNOI_FLAG. Left channel AGC noise-threshold flag 0: no noise-threshold 1: noise-threshold 19:12 R 0x0 ADAP_LCHAN_GAIN Left channel Gain applied by AGC (7.1format 2s component(-20dB – 40dB), 0.5dB/ step) 0x50 : 40dB 0x4F : 39.5dB --------------0x00 : 00dB 0xFF : -0.5dB 11:10 / / / 9 R 0x0 ADAP_RSATU_FLAG. Right AGC saturation flag 0 : no saturation 1: saturation 8 R 0x0 ADAP_RNOI_FLAG.
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System 0x1E: -84dB 0x1F: -86dB / / / 14 R/W 0x1 AAGC_LCHAN_EN. Left AGC function enable 0:disable 1: enable 13 R/W 0x1 ADAP_LHPF_EN. Left HPF enable 0: disable 1: enable 12 R/W 0x1 ADAP_RNOI_DET. Left Noise detect enable 0: disable 1:enable 11:10 / / / 9:8 R/W 0x0 ADAP_LCHAN_HYS. Left Hysteresis setting 00 : 1dB 01 : 2dB 10 : 4dB 11 : disable 7:4 R/W 0x0 3:0 R/W id e nt ia l 15 4.21.5.15. co nf ADAP_LNOI_DEB.
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System R/W 0x1F (-86dB) ADAP_RNOI_SET. Right channel noise threshold setting 0x00 : -24dB 0x01 : -26dB 0x02 : -28dB ---------------------0x1D: -82dB 0x1E: -84dB 0x1F: -86dB 15 / / / 14 R/W 0x1 AAGC_RCHAN_EN. Right AGC enable 0:disable 1:enable 13 R/W 0x1 ADAP_RHPF_EN. Right HPF enable 0: disable 1: enable 12 R/W 0x1 ADAP_RNOI_DET. Right Noise detect enable 0: disable 1:enable 11:10 / / 9:8 R/W 0x0 7:4 R/W id e nt ia l 20:16 / co nf ADAP_RCHAN_HYS.
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System 4.21.5.16. 0x7C ADC DAP Parameter Register(Default Value: 0x2C2C2828) Offset: 0x7C Register Name: AC_ADC_DAP_PARA R/W Default/Hex Description 31:30 / / / 29:24 R/W 0x2C ADAP_LTARG_SET. Left channel target level setting (-1dB -- -30dB). (6.0format 2s component) 23:22 / / / 21:16 R/W 0x2C ADAP_RTARG_SET. Right channel target level setting (-1dB -- -30dB). (6.0format 2s component) 15:8 R/W 0x28 ADAP_LGAIN_MAX. Left channel max gain setting (0-40dB). (7.
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System 0000 : 1x32/fs 0001 : 2x32/fs -----------------------7FFF : 215 x32/fs T=(n+1)*32/fs When the gain increases, the actual gain will increase 0.5dB at every decay time. 4.21.5.19. 0x88 ADC DAP Right Average Coef Register(Default Value: 0x00051EB8) Offset: 0x88 Register Name: AC_ADC_DAP_RAC R/W Default/Hex Description 31:27 / / / 26:0 R/W 0x0051EB8 ADAP_RAC. Average level coefficient setting(3.
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System 4.21.5.21. 0x90 ADC DAP HPF Coef Register(Default Value: 0x00FF_FAC1) Offset: 0x90 Register Name: AC_ADC_DAP_HPFC Bit R/W Default/Hex Description 31:27 / / / 26:0 R/W 0x0FFFAC1 ADAP_HPFC. HPF coefficient setting (3.24fomat) 4.21.5.22.
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System 01 : 0.9375db 10 : 1.9375db 11 : 3db / / / 5 R/W 0 The input signal average filter coefficient setting 0 : is the reg94/reg98 1 : is the reg80/reg88; 4 R/W 0 AGC output when the channel in noise state 0 : output is zero 1 : output is the input data 3 / / / 2 R/W 0 Right energy default value setting(include the input and output) 0 : min 1 : max 1 :0 R/W 00 Right channel gain hysteresis setting.
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System should write the drc delay function bit to 0; 0 : not complete 1 : is complete / / / 13:8 R/W 0 Signal delay time setting 6'h00 : (8x1)fs 6'h01 : (8x2)fs 6'h02 : (8x3)fs ---------------------------------------6'h2e : (8*47)fs 6'h2f : (8*48)fs 6'h30 -- 6'h3f : (8*48)fs Delay time = 8*(n+1)fs, n<6'h30; When the delay function is disable, the signal delay time is unused.
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System When the DRC LT is disable the LT, Kl and OPL parameter is unused. 0 R/W 4.21.5.28. DRC ET enable 0 : disable 1 : enable When the DRC ET is disable the ET, Ke and OPE parameter is unused.
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System 4.21.5.32. 0x11C DAC DRC Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF) Offset: 0x11C Register Name: AC_DAC_DRC_LPFHRT Bit R/W Default/Hex Description 15:11 / / / 10:0 R/W 0x00FF The left peak filter release time parameter setting, which determine by the equation that RT = exp(-2.2Ts/tr). The format is 3.24. (100ms) 4.21.5.33.
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System 4.21.5.37. 0x130 DAC DRC Left RMS Filter Low Coef Register(Default Value: 0x00002BAF) Offset: 0x130 Register Name: AC_DAC_DRC_LRMSLAT Bit R/W Default/Hex Description 15:0 R/W 0x2BAF The left RMS filter average time parameter setting, which determine by the equation that AT = 1-exp(-2.2Ts/tav). The format is 3.24. (10ms) 4.21.5.38.
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System 4.21.5.42. 0x144 DAC DRC Compressor Slope High Setting Register(Default Value: 0x00000080) Offset: 0x144 Register Name: AC_DAC_DRC_HKC Bit R/W Default/Hex Description 15:13 / / / 0x0080 The slope of the compressor which determine by the equation that Kc = 1/R, there, R is the ratio of the compressor, which always is interger. The format is 8.24. (2 : 1) R/W 0x148 DAC DRC Compressor Slope Low Setting Register(Default Value: 0x0000_0000) Offset: 0x148 15:0 R/W R/W 4.21.5.44.
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System 4.21.5.47. 0x158 DAC DRC Limiter Theshold Low Setting Register(Default Value: 0x0000_34F0) Offset: 0x158 Register Name: AC_DAC_DRC_LLT Bit R/W Default/Hex Description 15:0 R/W 0x34F0 The limiter threshold setting, which set by the equation that LTin = -LT/6.0206, The format is 8.24. (-10dB) 4.21.5.48.
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System 4.21.5.52. 0x16C DAC DRC Expander Theshold High Setting Register(Default Value: 0x00000BA0) Offset: 0x16C Register Name: AC_DAC_DRC_HET Bit R/W Default/Hex Description 15:0 R/W 0x0BA0 The expander threshold setting, which set by the equation that ETin = -ET/6.0206, The format is 8.24. (-70dB) 4.21.5.53.
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System 4.21.5.57. 0x180 DAC DRC Expander Low Output at Expander Threshold(Default Value: 0x00008D6E) Offset: 0x180 Register Name: AC_DAC_DRC_LOPE Bit R/W Default/Hex Description 15:0 R/W 0x8D6E The output of the expander which determine by equation OPE/6.0206. The format is 8.24 (-70dB) 4.21.5.58.
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System 4.21.5.62. 0x194 DAC DRC Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000) Offset: 0x194 Register Name: AC_DAC_DRC_SFHRT Bit R/W Default/Hex Description 15:11 / / / 10:0 R/W 0x0000 The gain smooth filter release time parameter setting, which determine by the equation that RT = 1-exp(-2.2Ts/tr). The format is 3.24. (200ms) 4.21.5.63.
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System 4.21.5.67. 0x1A8 DAC DRC MIN Gain Low Setting Register(Default Value: 0x00002C3F) Offset: 0x1A8 Register Name: AC_DAC_DRC_MNGLS Bit R/W Default/Hex Description 15:0 R/W 0x2C3F The min gain setting which determine by equation MNG/6.0206. The format is 8.24 and must -60dB ≤MNG ≤ -30dB (-40dB) 4.21.5.68.
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System 4.21.5.72. 0x200 ADC DRC High HPF Coef Register(Default Value: 0x000000FF) Offset: 0x200 Register Name: AC_ADC_DRC_HHPFC Bit R/W Default/Hex Description 15:11 / / / 10:0 R/W 0xFF HPF coefficient setting and the data is 3.24 format. 4.21.5.73. 0x204 ADC DRC Low HPF Coef Register(Default Value: 0x0000FAC1) Offset: 0x204 Register Name: AC_ADC_DRC_LHPFC R/W Default/Hex Description 15:0 R/W 0xFAC1 HPF coefficient setting and the data is 3.24 format.
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System 0 : disable 1 : enable 2 R/W 1 R/W R/W 0x0 Delay function enable 0 : disable 1 : enable When the Delay function enable is disable, the Signal delay time is unused. 0x0 DRC LT enable 0 : disable 1 : enable When the DRC LT is disable the LT, Kl and OPL parameter is unused. 0x0 DRC ET enable 0 : disable 1 : enable When the DRC ET is disable the ET, Ke and OPE parameter is unused.
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System 4.21.5.77. 0x214 ADC DRC Right Peak Filter High Attack Time Coef Register(Default Value: 0x0000_000B) Offset: 0x214 Register Name: AC_ADC_DRC_RPFHAT Bit R/W Default/Hex Description 15:11 / / / 10:0 R/W 0x000B The left peak filter attack time parameter setting, which determine by the equation that AT = 1-exp(-2.2Ts/ta). The format is 3.24. (1ms) 4.21.5.78.
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System 4.21.5.82. 0x228 ADC DRC Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8) Offset: 0x228 Register Name: AC_ADC_DRC_RPFLRT Bit R/W Default/Hex Description 15:0 R/W 0xE1F8 The left peak filter release time parameter setting, which determine by the equation that AT = exp(-2.2Ts/tr). The format is 3.24. (100ms) 4.21.5.83.
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System 4.21.5.87. 0x23C ADC DRC Compressor Theshold High Setting Register(Default Value: 0x000006A4) Offset: 0x23C Register Name: AC_ADC_DRC_HCT Bit R/W Default/Hex Description 15:0 R/W 0x06A4 The compressor threshold setting, which set by the equation that CTin = -CT/6.0206. The format is 8.24 (-40dB) 4.21.5.88.
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System 4.21.5.92. 0x250 ADC DRC Compressor Low Output at Compressor Threshold Register(Default Value: 0x00002C3F) Offset: 0x250 Register Name: AC_ADC_DRC_LOPC Bit R/W Default/Hex Description 15:0 R/W 0x2C3F The output of the compressor which determine by the equation OPC/6.0206 The format is 8.24 (-40dB) 4.21.5.93.
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System 4.21.5.97. 0x264 ADC DRC Limiter High Output at Limiter Threshold(Default Value: 0x0000FBD8) Offset: 0x264 Register Name: AC_ADC_DRC_HOPL Bit R/W Default/Hex Description 15:0 R/W 0xFBD8 The output of the limiter which determine by equation OPT/6.0206. The format is 8.24 (-25dB) 4.21.5.98.
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System 4.21.5.102. 0x278 ADC DRC Expander Slope Low Setting Register(Default Value: 0x00000000) Offset: 0x278 Bit 15:0 Register Name: AC_ADC_DRC_LKE R/W R/W 4.21.5.103. Default/Hex Description 0x0000 The slope of the expander which determine by the equation that Ke = 1/R, there, R is the ratio of the expander, which always is interger and the ke must larger than 50. The format is 8.24.
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System 4.21.5.107. 0x28C ADC DRC Smooth filter Gain High Attack Time Coef Register(Default Value: 0x00000002) Offset: 0x28C Register Name: AC_ADC_DRC_SFHAT Bit R/W Default/Hex Description 15:11 / / / 10:0 R/W 0x0002 The smooth filter attack time parameter setting, which determine by the equation that AT = 1-exp(-2.2Ts/tr). The format is 3.24. (5ms) 4.21.5.108.
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System 4.21.5.112. 0x2A0 ADC DRC MAX Gain Low Setting Register(Default Value: 0x0000CB0F) Offset: 0x2A0 Register Name: AC_ADC_DRC_MXGLS Bit R/W Default/Hex Description 15:0 R/W 0xCB0F The max gain setting which determine by equation MXG/6.0206. The format is 8.24 and must -20dB
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System 4.21.5.117. 0x2B8 ADC DRC HPF Gain High Coef Register(Default Value: 0x00000100) Offset: 0x2B8 Register Name: AC_ADC_DRC_HPFHGAIN Bit R/W Default/Hex Description 15:11 / / / 10:0 R/W 0x0100 The gain of the hpf coefficient setting which format is 3.24.(gain = 1) 4.21.5.118.
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System WDAT[7:0]：Write Data； RDAT[7:0]： Read Data. Reset APB0 W/R Addr[4:0] CPUS 0x01F015C0 Data_in[7:0] 25 8-bit registers Data_out[7:0] Bit 32-29 / 28 27-23 24 23-21 20-16 RST / WR / Addr 7-0 15-8 Data_in Data_out ia l Figure 4-16. Audio Codec Analog Register Diagram nt 4.21.6.2.
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System 4.21.6.4. 0x02 Right Output Mixer Source Select Control Register(Default Value: 0x00) Offset:0x02 Register Name: ROMIXSC R/W Default/Hex Description 7 / / / 6:0 R/W 0x0 RMIXMUTE Right Output Mixer Mute Control 0-Mute, 1-Not Mute Bit 6: MIC1 Boost Stage Bit 5: MIC2 Boost Stage Bit 4: / Bit 3: / Bit 2: LINEINR Bit 1: Right Channel DAC Bit 0: Left Channel DAC ia l Bit Offset:0x03 nt 4.21.6.5.
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System 3:0 / / / 4.21.6.7. 0x06 MIC1 And MIC2 Gain Control Register(Default Value: 0x33) Offset:0x06 Register Name: MIC_GCTR R/W Default/Hex Description 7 / / / 6:4 R/W 0x3 MIC1_GAIN MIC1 BOOST stage to L or R output mixer Gain Control From -4.5dB to 6dB, 1.5dB/step, default is 0dB 3 / / / 2:0 R/W 0x3 MIC2G, (volm2) MIC2 BOOST stage to L or R output mixer Gain Control From -4.5dB to 6dB, 1.5dB/step, default is 0dB ia l Bit Offset:0x07 nt 4.21.6.8.
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System 4.21.6.10.
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System Bit R/W Default/Hex Description 7 / / / 6:0 R/W 0x0 RADCMIXMUTE Right ADC Mixer Mute Control: 0-Mute, 1-Not Mute Bit 6: MIC1 Boost Stage Bit 5: MIC2 Boost Stage Bit 4: / Bit 3:/ Bit 2: LINEINL Bit 1: Left Output Mixer Bit 0: Right Output Mixer 0x0D Right ADC Mixer Source Control Register(Default Value: 0x00) Offset:0x0D ia l 4.21.6.13.
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System PA ANTI-POP Time Control 000: 131ms 001: 262ms 010: 393ms 011: 524ms 100: 655ms 101: 786ms 110: 917ms 111: 1048ms 4.21.6.15. 0x0F ADC Analog Part Enable Register(Default Value: 0x03) Offset:0x0F Register Name: ADC_AP_EN R/W Default/Hex Description 7 R/W 0x0 ADCREN ADC Right Channel Enable 0-Disable; 1-Enable 6 R/W 0x0 ADCLEN ADC Left Channel Enable 0-Disable; 1-Enable 5:3 / / / 2:0 R/W 0x3 ADCG ADC Input Gain Control From -4.5dB to 6dB, 1.
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System Bit R/W Default/Hex Description 7:6 R/W 0x1 OPMIC_BIAS_CUR OPMIC Bias Current Control 5:4 / / / 3:2 R/W 0x1 OPDAC_BIAS_CUR. OPDAC Bias Current Control 1:0 R/W 0x1 OPMIX_BIAS_CUR. OPMIX/OPLPF Bias Current Control 4.21.6.18.
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System ADC dither clock select 00: ADC FS * (8/9), about 43KHz when FS=48KHz 01: ADC FS * (16/15), about 51KHz when FS=48KHz 10: ADC FS * (4/3), about 64KHz when FS=48KHz 11: ADC FS * (16/9), about 85KHz when FS=48KHz R/W 4.21.6.20. 0x2 BIHE_CTRL, BIHE control 00: no BIHE 01: BIHE=7.5 HOSC 10: BIHE=11.5 HOSC 11: BIHE=15.
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System 4.21.6.22. 0x16 DA16 Register Setting Data Register(Default Value: 0x80) Offset:0x16 Register Name: DA16VERIFY Bit R/W Default/Hex Description 7:0 R/W 0x80 / 4.21.6.23. 0x17 Bias Calibration Data Register(Default Value: 0x20) Offset:0x17 Register Name: BIASCALI R/W Default/Hex Description 7:0 R 0x20 BIASCALI Bias Calibration Data, 6bit nt 0x18 Bias Register Setting Data Register(Default Value: 0x20) Offset:0x18 Register Name: BIASVERIFY id e 4.21.6.24.
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System 4.22. Port Controller(CPU-PORT) The chip has 7 ports for multi-functional input/out pins.
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System PG _INT_CTL 0x200+1*0x20+0x10 PIO Interrupt Control Register PG _INT_STA 0x200+1*0x20+0x14 PIO Interrupt Status Register PG _INT_DEB 0x200+1*0x20+0x18 PIO Interrupt Debounce Register 4.22.2. Port Controller Register Description 4.22.2.1.
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System 7 / / / 6:4 R/W 0x7 PA1_SELECT 000:Input 010:UART2_RX 100:Reserved 110:PA_EINT1 3 / / / 0x7 PA0_SELECT 000:Input 010:UART2_TX 100:Reserved 110:PA_EINT0 2:0 R/W Register Name: PA_CFG1_REG Bit R/W Default/Hex 31 / / 0x7 27 / / / PA15_SELECT 000:Input 010:SPI1_MOSI 100:Reserved 110:PA_EINT15 nf R/W Description co 30:28 26:24 R/W 0x7 PA14_SELECT 000:Input 010:SPI1_CLK 100:Reserved 110:PA_EINT14 23 / / / PA13_SELECT 000:Input 010:SPI1_CS 100:Reserved 110:PA_EINT13
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System / / 14:12 R/W 0x7 PA11_SELECT 000:Input 010:TWI0_SCK 100:Reserved 110:PA_EINT11 11 / / / PA10_SELECT 000:Input 010:SIM_DET 100:Reserved 110:PA_EINT10 0x7 7 / / 6:4 R/W 0x7 3 / / R/W 001:Output 011:Reserved 101:Reserved 111:IO Disable PA8_SELECT 000:Input 010:SIM_DATA 100:Reserved 110:PA_EINT8 001:Output 011:Reserved 101:Reserved 111:IO Disable 0x7 nf 2:0 PA9_SELECT 000:Input 010:SIM_RST 100:Reserved 110:PA_EINT9 nt R/W 001:Output 011:Reserved 101:Reserved 111:IO Disable
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System 010:PCM0_CLK 100:Reserved 110:PA_EINT19 / / PA18_SELECT 000:Input 010:PCM0_SYNC 100:Reserved 110:PA_EINT18 001:Output 011:TWI1_SCK 101:Reserved 111:IO Disable PA17_SELECT 000:Input 010:OWA_OUT 100:Reserved 110:PA_EINT17 001:Output 011:Reserved 101:Reserved 111:IO Disable 10:8 R/W 0x7 7 / / 6:4 R/W 0x7 3 / / R/W 001:Output 011:UART3_CTS 101:Reserved 111:IO Disable 0x7 id e 2:0 PA16_SELECT 000:Input 010:SPI1_MISO 100:Reserved 110:PA_EINT16 ia l / nt 11 011:TWI1_SDA 101:Reserv
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System 4.22.2.6. PA Multi-Driving Register 0 (Default Value: 0x55555555) Offset: 0x14 Bit [2i+1:2i] (i=0~15) Register Name: PA_DRV0_REG R/W R/W Default/Hex Description 0x1 PA_DRV PA[n] Multi-Driving Select (n = 0~15) 00: Level 0 01: Level 1 10: Level 2 11: Level 3 4.22.2.7.
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System PC Configure Register 0 (Default Value: 0x77777777) Offset: 0x48 Register Name: PC_CFG0_REG Bit R/W Default/Hex Description 31 / / / 30:28 R/W 0x7 PC7_SELECT 000:Input 010:NAND_RB1 100:Reserved 110:Reserved 27 / / / R/W 0x7 23 / / / PC5_SELECT 000:Input 010:NAND_RE 100:Reserved 110:Reserved 001:Output 011:SDC2_CMD 101:Reserved 111:IO Disable R/W 0x7 19 / / R/W 15 / 0x7 PC4_SELECT 000:Input 010:NAND_CE0 100:Reserved 110:Reserved co 18:16 / / 14:12 R/W 0x7 PC3
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System 100:Reserved 110:Reserved 2:0 / R/W 4.22.2.11.
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System R/W 0x7 7 / / / 6:4 R/W 0x7 PC9_SELECT 000:Input 010:NAND_DQ1 100:Reserved 110:Reserved 3 / / / 0x7 PC8_SELECT 000:Input 010:NAND_DQ0 100:Reserved 110:Reserved 4.22.2.12.
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System 4.22.2.14. PC Data Register (Default Value: 0x00000000) Offset: 0x58 Register Name: PC_DATA_REG Bit R/W Default/Hex Description 31:19 / / / 0x0 PC_DAT If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. R/W 4.22.2.15.
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System 4.22.2.18. PC PULL Register 1 (Default Value: 0x00000014) Offset: 0x68 Register Name: PC_PULL1_REG Bit R/W Default/Hex Description 31:6 / / Reserved 0x14 PC_PULL PC[n] Pull-up/down Select (n = 16~18) 00: Pull-up/down disable 01: Pull-up 10: Pull-down 11: Reserved [2i+1:2i] (i=0~2) R/W 4.22.2.19.
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System 110:Reserved 11 / / / 111:IO Disable 10:8 R/W 0x7 PD2_SELECT 000:Input 001:Output 010:RGMII_RXD1/MII_RXD1/RMII_RXD1 100:Reserved 101:Reserved 110:Reserved 111:IO Disable 7 / / / R/W 0x7 3 / / / 0x7 PD0_SELECT 000:Input 001:Output 010:RGMII_RXD3/ MII_RXD3/ RMII_NULL 100:Reserved 101:Reserved 110:Reserved 111:IO Disable 4.22.2.20.
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System 000:Input 001:Output 010:RGMII_TXCK/MII_TXCK/RMII_TXCK 100:Reserved 101:Reserved 110:Reserved 111:IO Disable 15 / / / 14:12 R/W 0x7 PD11_SELECT 000:Input 001:Output 010:RGMII_NULL/MII_CRS/RMII_NULL 100:Reserved 101:Reserved 110:Reserved 111:IO Disable 11 / / / R/W 0x7 7 / / / PD9_SELECT 000:Input 001:Output 010:RGMII_TXD1/MII_TXD1/RMII_TXD1 100:Reserved 101:Reserved 110:Reserved 111:IO Disable 3 / / R/W 4.22.2.21.
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System 110:Reserved 4.22.2.22. 111:IO Disable PD Configure Register 3 (Default Value: 0x00000000) Offset: 0x78 Register Name: PD_CFG3_REG Bit R/W Default/Hex Description 31:0 / / / 4.22.2.23. PD Data Register (Default Value: 0x00000000) Offset: 0x7C Register Name: PD_DATA _REG R/W Default/Hex Description 31:18 / / / 0x0 PD_DAT If the port is configured as input, the corresponding bit is the pin state.
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System 4.22.2.26. PD PULL Register 0 (Default Value: 0x00000000) Offset: 0x88 Bit [2i+1:2i] (i=0~15) Register Name: PD_PULL0_REG R/W R/W 4.22.2.27.
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System R/W 0x7 15 / / / 14:12 R/W 0x7 PE3_SELECT 000:Input 010:CSI_VSYNC 100: Reserved 110:Reserved 11 / / / R/W 0x7 7 / / / PE1_SELECT 000:Input 010:CSI_MCLK 100:Reserved 110:Reserved 001:Output 011:TS_DVLD 101:Reserved 111:IO Disable 001:Output 011:TS_SYNC 101:Reserved 111:IO Disable nt 10:8 PE2_SELECT 000:Input 010:CSI_HSYNC 100:Reserved 110:Reserved 001:Output 011:TS_D0 101:Reserved 111:IO Disable ia l 18:16 PE4_SELECT 000:Input 010: CSI_D0 100: Reserved 110:Reserved 0x7 3
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System 100: Reserved 110:Reserved / / / 22:20 R/W 0x7 PE13_SELECT 000:Input 010: CSI_SDA 100: Reserved 110:Reserved 19 / / / 18:16 R/W 0x7 PE12_SELECT 000:Input 010: CSI_SCK 100: Reserved 110:Reserved 15 / / / R/W 0x7 11 / / / 001:Output 011: TWI2_SCK 101:Reserved 111:IO Disable 001:Output 011: TS_D7 101:Reserved 111:IO Disable id e nt 14:12 PE11_SELECT 000:Input 010:CSI_D7 100: Reserved 110:Reserved 001:Output 011: TWI2_SDA 101:Reserved 111:IO Disable ia l 23 101:Reserved
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System 4.22.2.31. PE Configure Register 3 (Default Value: 0x00000000) Offset: 0x9C Register Name: PE_CFG3_REG Bit R/W Default/Hex Description 31:0 / / / 4.22.2.32. PE Data Register (Default Value: 0x00000000) Offset: 0xA0 Register Name: PE_DATA _REG R/W Default/Hex Description 31:16 / / / 0x0 PE_DAT If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit.
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System 00: Pull-up/down disable 10: Pull-down 4.22.2.36.
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System 110:Reserved 7 / / / 6:4 R/W 0x3 PF1_SELECT 000:Input 010:SDC0_D0 100:Reserved 110:Reserved 3 / / / 0x3 PF0_SELECT 000:Input 010:SDC0_D1 100:Reserved 110:Reserved R/W 001:Output 011:JTAG_MS 101:Reserved 111:IO Disable PF Configure Register 1 (Default Value: 0x00000000) ia l 4.22.2.38.
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System the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. 4.22.2.42. PF Multi-Driving Register 0 (Default Value: 0x00001555) Offset: 0xC8 Register Name: PF_DRV0_REG Bit R/W Default/Hex Description 31:14 / / / 0x1 PF_DRV PF[n] Multi-Driving SELECT (n = 0~6) 00: Level 0 01: Level 1 10: Level 2 11: Level 3 ia l R/W 4.22.2.43.
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System PG Configure Register 0 (Default Value: 0x77777777) Offset: 0xD8 Register Name: PG_CFG0_REG Bit R/W Default/Hex Description 31 / / / 30:28 R/W 0x7 PG7_SELECT 000:Input 010:UART1_RX 100:Reserved 110:PG_EINT7 27 / / / R/W 0x7 23 / / / PG5_SELECT 000:Input 010:SDC1_D3 100:Reserved 110:PG_EINT5 001:Output 011: Reserved 101:Reserved 111:IO Disable nt 26:24 PG6_SELECT 000:Input 010:UART1_TX 100:Reserved 110:PG_EINT6 001:Output 011: Reserved 101:Reserved 111:IO Disable ia l 4.
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System 100:Reserved 110:PG_EINT1 2:0 / R/W 4.22.2.47.
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System R/W 4.22.2.48. 0x7 PG Configure Register 2 (Default Value: 0x00000000) Offset: 0xE0 Register Name: PG_CFG2_REG Bit R/W Default/Hex Description 31:0 / / / PG Configure Register 3 (Default Value: 0x00000000) Offset: 0xE4 Register Name: PG_CFG3_REG R/W Default/Hex Description 31:0 / / / id e Bit 4.22.2.50. ia l 4.22.2.49. PG Data Register (Default Value: 0x00000000) Offset: 0xE8 Register Name: PG_DATA_REG R/W Default/Hex 31:14 / / 4.22.2.51.
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System 4.22.2.52. PG Multi-Driving Register 1 (Default Value: 0x00000000) Offset: 0xF0 Register Name: PG_DRV1_REG Bit R/W Default/Hex Description 31:0 / / / 4.22.2.53. PG PULL Register 0 (Default Value: 0x00000000) Offset: 0xF4 Register Name: PG_PULL0_REG R/W Default/Hex Description 31:28 / / / 0x0 PF_PULL PF[n] Pull-up/down Select (n = 0~13) 00: Pull-up/down disable 01: Pull-up 10: Pull-down 11: Reserved nt R/W 4.22.2.54.
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System [4i+3:4i] (i=0~7) R/W 4.22.2.57. EINT_CFG External INTn Mode (n = 8~15) 0x0: Positive Edge 0x1: Negative Edge 0x2: High Level 0x3: Low Level 0x4: Double Edge (Positive/ Negative) Others: Reserved 0 PA External Interrupt Configure Register 2 (Default Value: 0x00000000) Offset: 0x208 R/W Default/Hex Description 0 EINT_CFG External INTn Mode (n = 16~21) 0x0: Positive Edge 0x1: Negative Edge 0x2: High Level 0x3: Low Level 0x4: Double Edge (Positive/ Negative) Others: Reserved 4.22.2.58.
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System 4.22.2.60. PA External Interrupt Status Register (Default Value: 0x00000000) Offset: 0x214 Register Name: PA_EINT_STATUS_REG Bit R/W Default/Hex Description 31:24 / / / 0 EINT_STATUS External INTn Pending Bit (n = 0~21) 0: No IRQ pending 1: IRQ pending Write ‘1’ to clear R/W 4.22.2.61.
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System 4.22.2.63. PG External Interrupt Configure Register 1 (Default Value: 0x00000000) Offset: 0x224 Register Name: PG_EINT_CFG1_REG Bit R/W Default/Hex Description 31:24 / / / 0 EINT_CFG External INTn Mode (n = 8~13) 0x0: Positive Edge 0x1: Negative Edge 0x2: High Level 0x3: Low Level 0x4: Double Edge (Positive/ Negative) Others: Reserved 4.22.2.64.
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System 31:14 [n] (n=0~13) / R/W 4.22.2.68.
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System 4.23. Port Controller(CPUs-PORT) The chip has 1 port for multi-functional input/out pins. They are shown below:  Port L(PL):12 input/output port For various system configurations, these ports can be easily configured by software. All these ports can be configured as GPIO if multiplexed functions not used. The external PIO interrupt sources are supported and interrupt mode can be configured by software. 4.23.1.
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System R/W 0x7 27 / / / 26:24 R/W 0x7 PL6_SELECT 000:Input 010:S_JTAG_DO 100:Reserved 110:S_PL_EINT6 23 / / / R/W 0x7 19 / / / PL4_SELECT 000:Input 010:S_JTAG_MS 100:Reserved 110:S_PL_EINT4 001:Output 011:Reserved 101:Reserved 111:IO Disable 001:Output 011:Reserved 101:Reserved 111:IO Disable 18:16 R/W 0x7 15 / / id e nt 22:20 PL5_SELECT 000:Input 010:S_JTAG_CK 100:Reserved 110:S_PL_EINT5 001:Output 011:Reserved 101:Reserved 111:IO Disable ia l 30:28 PL7_SELECT 000:Input
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System 100:Reserved 110:S_PL_EINT0 101:Reserved 111:IO Disable 4.23.2.2.
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System 31:0 / / / 4.23.2.5. PL Data Register (Default Value: 0x00000000) Offset: 0x10 Register Name: PL_DATA_REG Bit R/W Default/Hex Description 31:12 / / / 0 PL_DAT If the port is configured as input, the corresponding bit is the pin state. If the port is configured as output, the pin state is the same as the corresponding bit. The read bit value is the value setup by software. If the port is configured as functional pin, the undefined value will be read. R/W ia l 11:0 4.23.2.6.
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System 4.23.2.9. PL PULL Register 1 (Default Value: 0x00000000) Offset: 0x20 Register Name: PL_PULL1 Bit R/W Default/Hex Description 31:0 / / / 4.23.2.10. PL External Interrupt Configure Register 0 (Default Value: 0x00000000) Offset: 0x200 Description 0 EINT_CFG External INTn Mode (n = 0~7) 0x0: Positive Edge 0x1: Negative Edge 0x2: High Level 0x3: Low Level 0x4: Double Edge (Positive/ Negative) Others: Reserved ia l Default/Hex R/W 4.23.2.11.
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System 4.23.2.13. PL External Interrupt Configure Register 3 (Default Value: 0x00000000) Offset: 0x20C Register Name: PL_EINT_CFG3 Bit R/W Default/Hex Description 31:0 / / / 4.23.2.14. PL External Interrupt Control Register (Default Value: 0x00000000) Offset: 0x210 Register Name: PL_EINT_CTL R/W Default/Hex Description 31:12 / / / 0 EINT_CTL External INTn Enable (n = 0~11) 0: Disable 1: Enable nt R/W 4.23.2.15.
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Memory Chapter 5 Memory This section describes the H3 memory from three aspects:    SDRAM NAND Flash SD/MMC 5.1.1. ia l 5.1. SDRAM Overview id e nt The SDRAM Controller (DRAMC) provides a simple, flexible, burst-optimized interface to all industy-standard SDRAM. It supports up to a 16G bits memory address space. nf The DRAMC automatically handles memory management, initialization, and refresh operations.
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Memory 5.2. NAND Flash 5.2.1. Overview The NDFC is the NAND Flash Controller which supports all NAND flash memory available in the market. New type flash can be supported by software re-configuration. The On-the-fly error correction code (ECC) is built-in NDFC for enhancing reliability. BCH is implemented and it can detect and correct up to 64 bits error per 512 or 1024 bytes data. The on chip ECC and parity checking circuitry of NDFC frees CPU for other tasks.
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Memory AHB Slave I/F Command FIFO DMA & INT Control FIFO Control FIFO RAM0 (256x32) ahb_clk domain Register File FIFO RAM1 (256x32) User Data (8x32) Normal Command FSM Spare Command FSM Batch Command FSM nt nfc_clk domain ia l Sync id e ECC Control nf NAND Flash Basic Operation RB[1:0] DO[7:0] DI[7:0] co CE[7:0] CLE ALE WE RE Figure 5-1. NDFC Block Diagram 5.2.3. NDFC Timing Diagram Typically, there are two kinds of serial access method.
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Memory NDFC_CLE t3 t4 NDFC_CE# NDFC_WE# t14 t12 sample n-1 sample 0 NDFC_RE# t13 NDFC_ALE t10 NDFC_RB# D(0) NDFC_IOx D(n-1) NDFC_CLE t3 NDFC_RE# NDFC_ALE NDFC_IOx sample 0 t13 t10 co NDFC_RB# t14 t12 t4 nf NDFC_WE# id e NDFC_CE# nt ia l Figure 5-2. Conventional Serial Access Cycle Diagram (SAM0) D(0) D(n-1) Figure 5-3. EDO type Serial Access after Read Cycle (SAM1) H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Memory NDFC_CLE t3 NDFC_CE# t14 NDFC_WE# sample 0 t12 NDFC_RE# t13 NDFC_ALE t10 NDFC_RB# NDFC_IOx D(0) D(n-1) NDFC_CLE NDFC_WE# NDFC_RE# t5 NDFC_IOx t11 t7 co NDFC_ALE t4 nf NDFC_CE# id e t3 t2 nt t1 ia l Figure 5-4. Extending EDO type Serial Access Mode (SAM2) t8 t9 COMMAND Figure 5-5. Command Latch Cycle H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Memory NDFC_CLE NDFC_CE# t1 t3 t4 t15 t6 NDFC_WE# t5 NDFC_RE# t11 t7 NDFC_ALE t8 NDFC_IOx t9 Addr(0) Addr(n-1) NDFC_CE# t3 NDFC_RE# t15 t5 t11 t7 co NDFC_ALE NDFC_IOx t4 t6 nf NDFC_WE# nt t1 id e NDFC_CLE ia l Figure 5-6. Address Latch Cycle t8 t9 D(0) D(n-1) Figure 5-7. Write Data to Flash Cycle H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Memory NDFC_CLE NDFC_CE# NDFC_WE# t12 t14 t13 NDFC_RE NDFC_ALE t16 NDFC_RB# NDFC_IOx D(0) CMD D(n-1) ia l Figure 5-8. Waiting R/B# ready Diagram nt NDFC_CLE id e NDFC_CE# NDFC_WE# t17 NDFC_ALE co NDFC_RB# nf NDFC_RE NDFC_IOx CMD D(0) D(n-1) Figure 5-9. WE# high to RE# low Timing Diagram H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Memory NDFC_CLE NDFC_CE# NDFC_WE# t18 NDFC_RE NDFC_ALE NDFC_RB# NDFC_IOx 05h Col1 Col2 D(n-2) D(n-1) ia l Figure 5-10. RE# high to WE# low Timing Diagram nt NDFC_CLE NDFC_CE# NDFC_ALE co NDFC_RB# id e NDFC_RE t19 nf NDFC_WE# NDFC_IOx Addr2 Addr3 D(0) D(1) D(2) Figure 5-11. Address to Data Loading Timing Diagram Timing cycle list: H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Memory t1 NDFC_CLE setup time 2T t2 NDFC_CLE hold time 2T t3 NDFC_CE setup time 2T t4 NDFC_CE hold time 2T t5 NDFC_WE# pulse width T t6 NDFC_WE# hold time T t7 NDFC_ALE setup time 2T t8 Data setup time T t9 Data hold time T t10 Ready to NDFC_RE# low 3T t11 NDFC_ALE hold time 2T t12 NDFC_RE# pulse width T t13 NDFC_RE# hold time T t14 Read cycle time 2T t15 Write cycle time 2T t16 NDFC_WE# high to R/B# busy T_WB t17 NDFC_WE# high to NDFC_RE# low T_WHR t18 N
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Memory 5.2.4. NDFC Operation Guide NDFC_CLE NDFC_CE# NDFC_WE# NDFC_RE Page Command cmdio[31:30]=2 NDFC_ALE NDFC_RB# NDFC_IOx 00h Address Cycle cmdio[18:16] cmdio[19]=1 30h Data output Second Command cmdio[24] Wait RB Signal cmdio[23] Sequence Read cmdio[20]=0 cmdio[25]=1 ia l First Command cmdio[22] cmdio[7:0] Addr(5 cycle) id e nt Figure 5-12.
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Memory NDFC_CLE NDFC_CE# NDFC_WE# NDFC_RE Page Command cmdio[31:30]=2 NDFC_ALE NDFC_RB# 00h NDFC_IOx First Command cmdio[22] cmdio[7:0] col0 col1 row0row1row2 30h Address Cycle cmdio[18:16] cmdio[19]=1 70h Second Command cmdio[24] Wait RB Signal cmdio[23] d(0) 00h Third Comand cmdio[28] Data output Forth Comand cmdio[29] Sequence Read cmdio[20]=0 cmdio[25]=1 ia l Figure 5-14.
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Memory 0x10 NDFC Timing Configure Register NDFC_ADDR_LOW 0x14 NDFC Low Word Address Register NDFC_ADDR_HIGH 0x18 NDFC High Word Address Register NDFC_BLOCK_NUM 0x1C NDFC Data Block Number Register NDFC_CNT 0x20 NDFC Data Counter for data transfer Register NDFC_CMD 0x24 Set up NDFC commands Register NDFC_RCMD_SET 0x28 Read Command Set Register for vendor’s NAND memory NDFC_WCMD_SET 0x2C Write Command Set Register for vendor’s NAND memory NDFC_ECC_CTL 0x34 ECC Configure and Control Re
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Memory DDR Repeat data mode 0: Lower byte 1: Higher byte 15 R/W R/W 14 R/W 13:12 / 0 NDFC_ALE_POL NDFC Address Latch Enable (ALE) Signal Polarity Select 0: High active 1: Low active 0 NDFC_DMA_TYPE 0: Dedicated DMA 1: Normal DMA 0 ia l 0 NDFC_CLE_POL NDFC Command Latch Enable (CLE) Signal Polarity Select 0: High active 1: Low active nt 16 R/W 0 NF_TYPE NAND Flash Type 0x0: Normal SDR NAND 0x1: Reserved 0x2: ONFI DDR NAND 0x3: Toggle DDR NAND id e 17 R/W 0 NDFC_RAM_METHOD Access inte
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Memory NDFC external R/B Signal select The value 0-3 selects the external R/B signal. The same R/B signal can be used for multiple chip select flash. R/W 1 R/W 0 R/W 0 0 NDFC_RESET NDFC Reset Write 1 to reset NDFC and clear to 0 after reset 0 NDFC_EN NDFC Enable Control 0: Disable NDFC 1: Enable NDFC 5.2.6.2.
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Memory 1: NAND Flash in READY State R / 7:5 / / / 0 NDFC_STA 0: NDFC FSM in IDLE state 1: NDFC FSM in BUSY state When NDFC_STA is 0, NDFC can accept new command and process command. 0 NDFC_CMD_FIFO_STATUS 0: Command FIFO not full and can receive new command 1: Full and waiting NDFC to process commands in FIFO Since there is only one 32-bit FIFO for command. When NDFC latches one command, command FIFO is free and can accept another new command.
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Memory 0: Disable 1: Enable 5.2.6.4. NDFC Timing Control Register(Default Value: 0x00000000) Offset: 0x0C Register Name: NDFC_TIMING_CTL Bit R/W Default/Hex Description 31:12 / / / R/W 0x0 7:6 / / / 0x0 NDFC_DC_CTL NDFC Delay Chain Control. (These bits are only valid in DDR data interface, and configure the relative phase between DQS and DQ[0…7] ) R/W nt id e 5:0 ia l 11:8 NDFC_READ_PIPE In SDR mode: 0: Normal 1: EDO 2: E-EDO Other : Reserved In DDR mode: 1~15 is valid.
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Memory 1: 8*2T 2: 16*2T 3: 31*2T 13:12 R/W 0 T_CS CE Setup Time 0: 2*2T 1: 8*2T 2: 16*2T 3: 31*2T 10:8 T_CAD Command, Address, Data Delay 000: 4*2T 001: 8*2T 010: 12*2T 011: 16*2T 100: 24*2T 101: 32*2T 110/111: 64*2T R/W 0x2 id e T_RHW RE# high to WE# low cycle number 00: 4*2T 01: 8*2T 10: 12*2T 11: 20*2T nf 0 co 7:6 R/W nt ia l 11 T_CDQSS DQS Setup Time for data input start 0: 8*2T 1: 24*2T 5:4 3:2 1:0 R/W R/W R/W H3 Datasheet(Revision1.
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Memory 11:38*2T 5.2.6.6.
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Memory Others: Reserved Notes: 1 data block = 512 or 1024 bytes main field data 5.2.6.9. NDFC Data Counter Register(Default Value: 0x00000000) Offset: 0x20 Register Name: NDFC_CNT Bit R/W Default/Hex Description 31:10 / / / 0 NDFC_DATA_CNT Transfer Data Byte Counter The length can be set from 1 byte to 1024 bytes. However, 1024 bytes is set when it is zero. R/W ia l 9:0 5.2.6.10.
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Memory fetching data from Flash. If this bit is set to 0, NDFC output the data in internal RAM or do nothing after fetching data from Flash.
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Memory This command will be sent to external Flash by NDFC. 5.2.6.11.
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Memory 10 R/W R/W 0x4a80 NDFC_RANDOM_SEED The seed value for randomize engine. It is only active when NDFC_RANDOM_EN is set to ‘1’.
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Memory 5.2.6.15. NDFC ECC Status Register(Default Value: 0x00000000) Offset: 0x38 31:16 R R Default/Hex Description 0 NDFC_PAT_FOUND Special pattern (all 0x00 or all x0ff) Found Flag for 16 Data Blocks 0: No Found 1: Special pattern is found When this field is ‘1’, this means that the special data is found for reading external NAND flash. The register of NDFC_PAT_ID would indicates which pattern is found.
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Memory (i=0~3) ECC Corrected Bits Number for ECC Data Block[n] (n from 0 to 3) 0: No corrected bits 1: 1 corrected bit 2: 2 corrected bits … 64: 64 corrected bits Others: Reserved Notes: 1 ECC Data Block = 512 or 1024 bytes 5.2.6.18.
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Memory ECC_COR_NUM ECC Corrected Bits Number for ECC Data Block[n] (n from 12 to 15) 0: No corrected bits 1: 1 corrected bit 2: 2 corrected bits … 64: 64 corrected bits Others: Reserved Notes: 1 ECC Data Block = 512 or 1024 bytes [8i+7:8i] (i=0~3) R 0 5.2.6.21.
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Memory Bit [2i+1:2i] (i=0~15) R/W R Default/Hex Description 0 PAT_ID Special Pattern ID for 16 ECC data block 0: All 0x00 is found 1: All 0xFF is found Others: Reserved 5.2.6.25. NDFC Read Data Status Control Register(Default Value: 0x01000000) Offset: 0xA8 Register Name: NDFC_RDATA_STA_CTL Bit R/W Default/Hex 31:25 / / / Description R/W 1 23:18 / / / 0 id e nf R/W NDFC_RDATA_STA_TH The threshold value to generate data status.
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Memory automatically when next command is executed. 5.2.6.28. NDFC MBUS DMA Address Register(Default Value: 0x00000000) Offset: 0xC0 Bit 31:0 Register Name: NDFC_MDMA_ADDR R/W R/W Default/Hex Description 0 MDMA_ADDR MBUS DMA address 5.2.6.29. NDFC MBUS DMA Byte Counter Register(Default Value: 0x00000000) Offset: 0xC4 Register Name: NDFC_MDMA_CNT R/W Default/Hex Description 14:0 R/W 0 MDMA_CNT MBUS DMA data counter co nf id e nt ia l Bit H3 Datasheet(Revision1.
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Memory 5.3. SD/MMC 5.3.1. Overview The SD/MMC controller can be configured either as a Secure Digital Multimedia Card controller, which simultaneously supports Secure Digital memory (SD Memory), Secure Digital I/O (SDIO), Multimedia Cards (MMC), eMMC Card. co nf id e nt ia l The SD/MMC controller includes the following features:  Supports Secure Digital memory protocol commands (up to SD2.0)  Supports Secure Digital I/O protocol commands  Supports Multimedia Card protocol commands (up to eMMC4.
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Memory 5.3.2. Block Diagram SD/MMC Controller Timing Diagram Please refer to relative specifications: nf Physical Layer Specification Ver2.00 Final SDIO Specification Ver2.00 Multimedia Cards (MMC – version 4.2) JEDEC Standard – JESD84-44, EMBEDDED MULTI-MEDIA CARD (e•MMC) 5.3.4. co     id e 5.3.3. nt ia l Figure 5-16. SD/MMC Controller Block Diagram SD/MMC Controller Special Requirement 5.3.4.1.
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Memory Internal DMA Controller Description nt 5.3.5. ia l Figure 5-17. SD/MMC Pin Diagram nf id e SD/MMC controller has an internal DMA controller (IDMAC) to transfer data between host memory and SDMMC port. With a descriptor, IDMAC can efficiently move data from source to destination by automatically loading next DMA transfer arguments, which need less CPU intervention.
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Memory 5.3.5.2. DES0 definition 31 Descriptor HOLD DES_OWN_FLAG When set, this bit indicates that the descriptor is owned by the IDMAC. When this bit is reset, it indicates that the descriptor is owned by the host. This bit is cleared when transfer is over. ERROR 29:6 / 5 / ERR_FLAG When some error happened in transfer, this bit will be set.
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Memory 5.3.5.3. DES1 definition Bits Name Descriptor 31:16 / / Buffer size BUFF_SIZE These bits indicate the data buffer byte size, which must be a multiple of 4 bytes. If this filed is 0, the DMA ignores this buffer and proceeds to the next descriptor. 15:0 5.3.5.4. DES2 definition Descriptor Buffer address pointer BUFF_ADDR These bits indicate the physical address of data buffer. The IDMAC ignores DES2[1:0], corresponding to the bus width of 32. ia l 31:0 Name nt Bits Bits id e 5.3.5.5.
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Memory 0x24 Response 1 register SD_RESP2 0x28 Response 2 register SD_RESP3 0x2C Response 3 register SD_IMKR 0x30 Interrupt mask register SD_MISR 0x34 Masked interrupt status register SD_RISR 0x38 Raw interrupt status register SD_STAR 0x3C Status register SD_FWLR 0x40 FIFO Water Level register SD_FUNS 0x44 FIFO Function Select register SD_A12A 0x58 Auto command 12 argument SD_NTSR 0x5C SD NewTiming Set Register SD_SDBG 0x60 SD NewTiming Set Debug Register SD_HWRST 0x78 Ha
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Memory 10 R/W 0 DDR_MOD_SEL DDR Mode Select 0 – SDR mode 1 – DDR mode 9 - - reserved 8 R/W 1 CD_DBC_ENB Card Detect (Data[3] status) De-bounce Enable 0 - disable de-bounce 1 – enable de-bounce 7:6 - - / 0 DMA_ENB DMA Global Enable 0 – Disable DMA to transfer data, using AHB bus 1 – Enable DMA to transfer data 5 R/W R/W 0 3 - - / 2 R/W 0 DMA_RST DMA Reset nt id e R/W 0 FIFO_RST FIFO Reset 0 – No change 1 – Reset FIFO This bit is auto-cleared after completion of reset operat
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Memory 16 R/W 0 CCLK_ENB Card Clock Enable 0 – Card Clock off 1 – Card Clock on 15:8 / / / 0 CCLK_DIV Card clock divider n – Source clock is divided by 2*n.(n=0~255) 7:0 R/W 5.3.7.3.
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Memory 5.3.7.6. SD Block Count Register (Default Value: 0x00000200) Offset: 0x0014 Bit 31:0 Register Name: SD_BYTCNT R/W R/W Default/Hex Description 0x200 BYTE_CNT Byte counter Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. 5.3.7.7. SD Command Register (Default Value: 0x00000000) Offset: 0x0018 Description CMD_LOAD Start Command. This bit is auto cleared when current command is sent.
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Memory R/W 0 20:16 / / / 0 SEND_INIT_SEQ Send Initialization 0 – normal command sending 1 – Send initialization sequence before sending this command. 0 STOP_ABT_CMD Stop Abort Command 0 – normal command sending 1 – send Stop or abort command to stop current data transfer in progress.
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Memory 0 – Command without Response 1 – Command with Response 5:0 R/W CMD_IDX CMD Index Command index value 0 5.3.7.8. SD Command Argument Register (Default Value: 0x00000000) Register Name: SD_CMDARG Bit R/W Default/Hex Description 31:0 R/W 0 CMD_ARG Command argument 5.3.7.9.
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Memory 5.3.7.12. SD Response 3 Register (Default Value: 0x00000000) Offset: 0x002C Register Name: SD_RESP3 Bit R/W Default/Hex Description 31:0 R 0 CMD_RESP3 response 3 Bit[127:96] of response 5.3.7.13.
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Memory MSKD_ISTA Interrupt status. Enabled only if corresponding bit in mask register is set. R 0 nf id e nt ia l 31:0 Bit field defined as following: bit 31 – card removed bit 30 – card inserted bit 17~29 - reserved bit 16 – SDIO interrupt bit 15 – Data End-bit error bit 14 – Auto command done bit 13 – Data Start Error bit 12 – Command Busy and illegal write bit 11 – FIFO under run/overflow bit 10 – Data starvation timeout (HTO)/V1.
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Memory bit 9 – Data timeout/Boot data start bit 8 – Response timeout/Boot ACK received bit 7 – Data CRC error bit 6 – Response CRC error bit 5 – Data Receive Request bit 4 –Data Transmit Request bit 3 – Data Transfer Complete bit 2 – Command Complete bit 1 – Response Error (no response or response CRC error) bit 0 – Reserved 5.3.7.16.
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Memory 4 – Tx cmd index + arg 5 – Tx cmd crc7 6 – Tx cmd end bit 7 – Rx resp start bit 8 – Rx resp IRQ response 9 – Rx resp tx bit 10 – Rx resp cmd idx 11 – Rx resp data 12 – Rx resp crc7 13 – Rx resp end bit 14 – Cmd path wait NCC 15 – Wait; CMD-to-response turnaround R 0 1 FIFO_EMPTY FIFO Empty 1 - FIFO Empty 0 - FIFO not Empty 1 FIFO_TX_LEVEL FIFO TX Water Level flag 0 – FIFO didn’t reach transmit trigger level 1 - FIFO reached transmit trigger level R 0 FIFO_RX_LEVEL FIFO TX Water Level flag 0
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Memory Should be programmed same as DMA controller multiple transaction size. The units for transfers are the DWORD. A single transfer would be signaled based on this value. Value should be sub-multiple of (RX_TL + 1) and (FIFO_DEPTH - TX_TL) Recommended: MSize = 8, TX_TL = 16, RX_TL = 15 27:21 R 0 / R/W 0xF 15:5 R 0 / 0 TX_TL TX Trigger Level 0x1~0xf – TX Trigger Level is 1~31 0x0 – no trigger FIFO threshold when FIFO requests host to transmit data to FIFO.
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Memory Read Wait 0 – Clear SDIO read wait 1 – Assert SDIO read wait 0 R/W HOST_SEND_MMC_IRQRESQ Host Send MMC IRQ Response 0 – Ignored 1 – Send auto IRQ response When host is waiting MMC card interrupt response, setting this bit will make controller cancel wait state and return to idle state, at which time, controller will receive IRQ response sent by itself. This bit is auto-cleared after response is sent. 0 Offset: 0x0058 ia l 5.3.7.19.
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Memory 5.3.7.21. SD Hardware Reset Register (Default Value: 0x00000001) Offset: 0x0078 Register Name: SD_HWRST Bit R/W Default/Hex Description 31:1 / / / 1 HW_RESET. 1 – Active mode 0 – Reset These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. 0 R/W 5.3.7.22.
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Memory Specifies the number of Word to skip between two unchained descriptors. This is applicable only for dual buffer structure. Default is set to 4 DWORD. 1 0 R/W R/W 0 FIX_BUST_CTRL Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. 0 IDMAC_RST DMA Reset.
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Memory Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt. 3’b001 – Host Abort received during transmission 3’b010 – Host Abort received during reception Others: Reserved EB is read-only. R/W 0 NOR_INT_SUM Normal Interrupt Summary. Logical OR of the following: IDSTS[0] – Transmit Interrupt IDSTS[1] – Receive Interrupt Only unmasked bits affect this bit.
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Memory 1 0 R/W R/W 0 RX_INT Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit. 0 TX_INT Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a ‘1’ clears this bit. 5.3.7.25. SD DMAC Interrupt Enable Register (Default Value: 0x00000000) Offset: 0x008C Register Name: SD_IDIE_REG R/W Default/Hex Description 31:10 / / / 0 ABN_INT_ENB Abnormal Interrupt Summary Enable.
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Memory enabled. When reset, Receive Interrupt is disabled. 0 R/W TX_INT_ENB Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. 0 5.3.7.26.
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Memory Response CRC Response CRC from card/eMMC. 5.3.7.29. SD Data7 CRC Register (Default Value: 0x00000000) Offset: 0x0114 31:0 R/W R Default/Hex Description 0 DATA7_CRC Data[7] CRC CRC in data[7] from card/eMMC.In DDR mode,the higher 16 bits indicate the CRC of even data,and the lower 16bits indicate the CRC of odd data.In SDR mode,the higher of 16 bits indicate the CRC of all data. 5.3.7.30.
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Memory CRC in data[4] from card/eMMC.In DDR mode,the higher 16 bits indicate the CRC of even data,and the lower 16bits indicate the CRC of odd data.In SDR mode,the higher of 16 bits indicate the CRC of all data. 5.3.7.33. SD Data3 CRC Register (Default Value: 0x00000000) Offset: 0x0124 Bit R/W R Default/Hex Description 0 DATA3_CRC Data[3] CRC CRC in data[3] from card/eMMC. In 8bit DDR mode,the higher 16 bits indicate the CRC of even data,and the lower 16bits indicate the CRC of odd data.
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Memory In SDR mode,the higher of 16 bits indicate the CRC of all data. 5.3.7.36. SD Data0 CRC Register (Default Value: 0x00000000) Offset: 0x0130 31:0 R/W R Default/Hex Description 0 DATA0_CRC Data[0] CRC CRC in data[0] from card/eMMC. In 8bit DDR mode,the higher 16 bits indicate the CRC of even data,and the lower 16bits indicate the CRC of odd data. In 4 bit DDR mode,the higher of 16 bits indicate the CRC of odd data, ,and the lower 16bits indicate the CRC of even data.
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Image Chapter 6 Image This section describes the image input of H3:  CSI 6.1.1. ia l 6.1.
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Image 6.1.2. Functionalities Description 6.1.2.1. Block Diagram CS Data Clock FIFO 2 FIFO 1 CSI Formatter FIFO 0 Channel 0 CS Vsync CS Data CSI IF Converter YUV Interleaved/Raw IF MUX CCIR656 IF CS Field ia l System BUS CS Hsync DMA nt Pattern Generater id e DMA co nf Figure 6-1. CSI Block Diagram SDA CTL CCI FIFO 24MHz CLK SDA PAD CTL CLD_DIV SCL CTL SCL FMT CTL DLY CNT CSI0/1 1st HREF CSI0/1 last HREF CSI0/1 Line counter CSI TRIG REGISTER IMMEDIATELY TRIG SEL Figure 6-2.
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Image 6.1.2.2. CSI FIFO Distribution Interface YUYV422 Interleaved/Raw Input format BT656 Interface YUV422 Raw YUV422 Output format Planar UV combined/ MB Raw/RGB/PRGB Planar UV combined/MB CH0_FIFO0 Y pixel data Y pixel data All pixels data Y Y CH0_FIFO1 Cb (U) pixel data Cb (U) Cr (V) pixel data - Cb (U) CbCr (UV) CH0_FIFO2 Cr (V) pixel data - Cr (V) 6.1.2.3.
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Image 6.1.2.4. Bit Definition CCIR656 Header Data Bit Definition: First Word(0xFF) Second Word(0x00) Third Word(0x00) Fourth Word CS D[9] (MSB) 1 0 0 1 CS D[8] 1 0 0 F CS D[7] 1 0 0 V CS D[6] 1 0 0 H CS D[5] 1 0 0 P3 CS D[4] 1 0 0 P2 CS D[3] 1 0 0 P1 CS D[2] 1 0 0 P0 CS D[1] x x x x CS D[0] x x x x ia l Data Bit Note: For compatibility with 8-bit interface, CS D[1] and CS D[0] are not defined.
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0X004C CSI Channel_0 scale register CSI0_C0_F0_BUFA_REG 0X0050 CSI Channel_0 FIFO 0 output buffer-A address register CSI0_C0_F1_BUFA_REG 0X0058 CSI Channel_0 FIFO 1 output buffer-A address register CSI0_C0_F2_BUFA_REG 0X0060 CSI Channel_0 FIFO 2 output buffer-A address register CSI0_C0_CAP_STA_REG 0X006C CSI Channel_0 status register CSI0_C0_INT_EN_REG 0X0070 CSI Channel_0 interrupt enable register CSI0_C0_INT_STA_REG 0X0074 CSI Channel_0 interrupt status register CSI0_C0_HSIZE_REG 0X00
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Image 1: SRAM in power down / / / 4 R/W 0x0 PTN_START CSI Pattern Generating Start 0: Finish other: Start Software write this bit to“1” to start pattern generating from DRAM. When finished, the hardware will clear this bit to“0”automatically. Generating cycles depends on PTN_CYCLE.
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Image 0: negative 1: positive This register is not apply to CCIR656 interface. R/W 0 HERF_POL Href polarity 0: negative 1: positive This register is not apply to CCIR656 interface.
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Image If video capture is in progress, the CSI stops capturing image data at the end of the current frame, and all of the current frame data is wrote to output FIFO. 1: Enable video capture The CSI starts capturing image data at the start of the next frame. 0 R/W 0x0 CH0_SCAP_ON Still capture control: Capture a single still image frame on channel 0. 0: Disable still capture. 1: Enable still capture The CSI module starts capturing image data at the start of the next frame.
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Image 6.1.4.6. CSI Pattern Generation Length Register (Default Value: 0x00000000) Offset: 0x0030 Register Name: CSI0_PTN_LEN_REG Bit R/W Default/Hex Description 31:0 R/W 0x0 PTN_LEN The pattern length in byte when generating pattern. 6.1.4.7. CSI Pattern Generation Address Register (Default Value: 0x00000000) Offset: 0x0034 Register Name: CSI0_PTN_ADDR_REG R/W Default/Hex Description 31:0 R/W 0x0 PTN_ADDR The pattern DRAM address when generating pattern. Offset: 0x003C nt 6.1.4.8.
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Image 0000: field-raw-8 0001: field-raw-10 0010: field-raw-12 0011: reserved 0100: field-rgb565 0101: field-rgb888 0110: field-prgb888 1000: frame-raw-8 1001: frame-raw-10 1010: frame-raw-12 1011: reserved 1100: frame-rgb565 1101: frame-rgb888 1110: frame-prgb888 co nf id e nt ia l When the input format is set YUV422 0000: field planar YCbCr 422 0001: field planar YCbCr 420 0010: frame planar YCbCr 420 0011: frame planar YCbCr 422 0100: field planar YCbCr 422 UV combined 0101: field planar YCbCr 420 U
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Image 1011: Reserved 1100: Reserved 1101: field planar YCbCr 420 10bit UV combined 1110: Reserved 1111: Reserved Others: reserved / / / 13 R/W 0 VFLIP_EN Vertical flip enable When enabled, the received data will be arranged in vertical flip. 0:Disable 1:Enable 12 R/W 0 HFLIP_EN Horizontal flip enable When enabled, the received data will be arranged in horizontal flip. 0:Disable 1:Enable 11:10 R/W 0 FIELD_SEL Field selection. 00: capturing with field 1. 01: capturing with field 2.
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Image 6.1.4.10. CSI Channel_0 scale Register (Default Value: 0x00000000) Offset: 0x004C Register Name: CSI0_C0_SCALE_REG Bit R/W Default/Hex Description 31:01 / / / 00 R/W 0 QUART_EN When this bit is set to 1, input image will be decimated to quarter size. All input format are supported. 6.1.4.11.
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Image 01 R 0 VCAP_STA Video capture in progress Indicates the CSI is capturing video image data (multiple frames). The bit is set at the start of the first frame after enabling video capture. When software disables video capture, it clears itself after the last pixel of the current frame is captured. 00 R 0 SCAP_STA Still capture in progress Indicates the CSI is capturing still image data (single frame). The bit is set at the start of the first frame after enabling still frame capture.
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Image 00 R/W 0 CD_INT_EN Capture done Indicates the CSI has completed capturing the image data. For still capture, the bit is set when one frame data has been wrote to buffer. For video capture, the bit is set when the last frame has been wrote to buffer after video capture has been disabled. For CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means field end. 6.1.4.16.
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Image 6.1.4.18. CSI Channel_0 vertical size Register (Default Value: 0x01E00000) Offset: 0x0084 Register Name: CSI0_C0_VSIZE_REG Bit R/W Default/Hex Description 31:29 / / / 28:16 R/W 1E0 VER_LEN Vertical line length. Valid line number of a frame. 15:13 / / / 12:00 R/W 0 VER_START Vertical line start. data is valid from this line. Offset: 0x0088 ia l 6.1.4.19.
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Image 23:00 R 0 FRM_CLK_CNT Counter value between every frame. For instant hardware frame rate statics. The internal counter is added by one every 24MHz clock cycle. When frame done or vsync comes, the internal counter value is sampled to FRM_CLK_CNT, and cleared to 0. 6.1.4.22.
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Image 15 / / / 14:00 R 0x7fff PCLK_CNT_LINE_MIN Indicates minimum pixel clock counter value for each line. Update at every vsync or framedone. 6.1.4.25. CCI Control Register (Default Value: 0x00000000) Offset: 0x3000 Register Name: CCI_CTRL_REG R/W Default/Hex Description 31 R/W 0 SINGLE_TRAN 0: Transmission idle 1: Start single transmission Automatically cleared to ‘0’ when finished. Abort current transmission immediately if changing from ‘1’ to ‘0’.
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Image 15:2 / / / 1 R/W 0 SOFT_RESET 0: normal 1: reset 0 R/W 0 CCI_EN 0: Module disable 1: Module enable ia l 0x28: Data byte transmitted in master mode, ACK received 0x30: Data byte transmitted in master mode, ACK not received 0x38: Arbitration lost in address or data byte 0x40: Address + Read bit transmitted, ACK received 0x48: Address + Read bit transmitted, ACK not received 0x50: Data byte received in master mode, ACK received 0x58: Data byte received in master mode, ACK not received 0x01:
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Image 0001: Last HREF done 0010: Line counter trigger other: Reserved 6.1.4.27. CCI Packet Format Register (Default Value: 0x00110001) Offset: 0x3008 Register Name: CCI_FMT_REG R/W Default/Hex Description 31:25 R/W 0 SLV_ID 7bit address 24 R/W 0 CMD 0: write 1: read 23:20 R/W 1 ADDR_BYTE How many bytes be sent as address 0~15 19:16 R/W 1 DATA_BYTE How many bytes be sent/received as data 1~15 Normally use ADDR_DATA with 0_2, 1_1, 1_2, 2_1, 2_2 access mode.
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Image SDA current status R/W 0 SCL_PEN SCL PAD enable 4 R/W 0 SDA_PEN SDA PAD enable 3 R/W 0 SCL_MOV SCL manual output value 2 R/W 0 SDA_MOV SDA manual output value 1 R/W 0 SCL_MOE SCL manual output en 0 R/W 0 SDA_MOE SDA manual output en ia l 5 6.1.4.29.
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Display Chapter 7 Display This chapter describes the H3 display system from following perspectives:   DE2.0 TCON co nf id e nt ia l The following figure shows the block diagramof display system: Figure 7-1. Display System Block Diagram H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Display 7.1. DE2.0 7.1.1.
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Display 7.2. TCON 7.2.1. Overview The LCD0 module is used for HDMI, and LCD1 module is used for TV.  Support HDMI interface, up to 4K  Support TV interface, up to 480P/576P  2 interrupts for programmer single TCON output Block Diagram co nf id e nt ia l 7.2.2. Figure 7-2. TCON Block Diagram 7.2.3. Functionalities Description 7.2.3.1. RGB gamma correction Function: This module correct the RGB input data of DE0 . A 256*8*3 Byte register file is used to store the gamma table.
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Display ...... ...... 0x4FC { B255[7:0], G255[7:0], R255[7:0] } LCD0 Module Register List id e 7.2.4. nt Function: This module enhance color data from DE0 . R’ = Rr*R + Rg*G + Rb*B + Rc G’ = Gr*R + Gg*G + Gb*B +Gc B’ = Br*R + Bg*G + Bb*B + Bc Note: Rr, Rg, Rb, ,Gr, Gg, Gb, Br, Bg, Bb s13 (-16,16) Rc, Gc, Bc s19 (-16384, 16384) R, G, B u8 [0-255] R’ have the range of [Rmin ,Rmax] G’ have the range of [Rmin ,Rmax] B’ have the range of [Rmin ,Rmax] ia l 7.2.3.2.
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Display 0x140+N*0x04 TCON CEU coefficient register2 (N=0,1,2) TCON_SAFE_PERIOD_REG 0x1F0 TCON safe period register TCON1_FILL_CTL_REG 0x300 TCON1 fill data control register TCON1_FILL_BEGIN_REG 0x304+N*0x0C TCON1 fill data begin register (N=0,1,2) TCON1_FILL_END_REG 0x308+N*0x0C TCON1 fill data end register (N=0,1,2) TCON1_FILL_DATA0_REG 0x30C+N*0x0C TCON1 fill data value register (N=0,1,2) TCON1_GAMMA_TABLE_REG 0x400-0x7FF TCON_ECC_FIFO_BIST_REG 0xFFC 7.2.5.
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Display 14 R/W 0 TCON1_Vb_Int_Flag Asserted during vertical no-display period every frame. Write 0 to clear it. 13 / / / 12 R/W 0 TCON1_Line_Int_Flag trigger when SY1 match the current TCON1 scan line Write 0 to clear it. 11:0 / 0 / 7.2.5.3.
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Display source width is X+1 15:12 / / / 11:0 R/W 0 TCON1_YI source height is Y+1 7.2.5.6. TCON1 Basic Timing Register1 (Default Value: 0x00000000) Offset: 0x098 Register Name: TCON1_BASIC1_REG R/W Default/Hex Description 31:28 / / / 27:16 R/W 0 LS_XO width is LS_XO+1 15:12 / / / 11:0 R/W 0 LS_YO width is LS_YO+1 NOTE: This version LS_YO = TCON1_YI nt ia l Bit Offset: 0x09C id e 7.2.5.7.
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Display 7.2.5.9. TCON1 Basic Timing Register4 (Default Value: 0x00000000) Offset: 0x0A4 Register Name: TCON1_BASIC4_REG Bit R/W Default/Hex Description 31:29 / / / 28:16 R/W 0 VT horizontal total time (in HD line) Tvt = VT/2 * Th 15:12 / / / 11:0 R/W 0 VBP horizontal back porch (in HD line) Tvbp = (VBP +1) * Th Offset: 0x0A8 ia l 7.2.5.10.
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Display (N=0,1,2,4,5,6,8,9,10) R/W Default/Hex Description 31:13 / / / 12:0 R/W 0 CEU_Coef_Mul_Value signed 13bit value, range of (-16,16) N=0: Rr N=1: Rg N=2: Rb N=4: Gr N=5: Gg N=6: Gb N=8: Br N=9: Bg N=10: Bb ia l Bit Register Name: TCON_CEU_COEF_ADD_REG Bit R/W Default/Hex 31:19 / / 18:0 R/W 0 Description id e Offset: 0x11C+N*0x10 (N=0,1,2) nt 7.2.5.13.
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Display 7.2.5.15. TCON1 Fill Control Register (Default Value: 0x00000000) Offset: 0x300 Register Name: TCON1_FILL_CTL_REG Bit R/W Default/Hex Description 31 R/W 0 TCON1_Fill_En 0: bypass 1: enable 30:0 / / / 7.2.5.16. TCON1 Fill Begin Register (Default Value: 0x00000000) Register Name: TCON1_FILL_BEGIN_REG R/W Default/Hex Description 31:24 / / / 23:0 R/W 0 Fill_Begin nt Bit ia l Offset: 0x304+N*0x0C (N=0,1,2) Offset: 0x308+N*0x0C (N=0,1,2) id e 7.2.5.17.
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Display 0x000 TCON global control register TCON_GINT0_REG 0x004 TCON global interrupt register0 TCON_GINT1_REG 0x008 TCON global interrupt register1 TCON1_CTL_REG 0x090 TCON1 control register TCON1_BASIC0_REG 0x094 TCON1 basic timing register0 TCON1_BASIC1_REG 0x098 TCON1 basic timing register1 TCON1_BASIC2_REG 0x09C TCON1 basic timing register2 TCON1_BASIC3_REG 0x0A0 TCON1 basic timing register3 TCON1_BASIC4_REG 0x0A4 TCON1 basic timing register4 TCON1_BASIC5_REG 0x0A8 TCON1 bas
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Display 30 R/W 0 TCON_Gamma_En 0: disable 1: enable 29:0 / / / 7.2.7.2. TCON Global Interrupt Register0 (Default Value: 0x00000000) Offset: 0x0004 Register Name: TCON_GINT0_REG R/W Default/Hex Description 31 / / / 30 R/W 0 TCON1_Vb_Int_En 0: disable 1: enable 29 / / / 28 R/W 0 TCON1_Line_Int_En 0: disable 1: enable 27:15 / / / 14 R/W 0 TCON1_Vb_Int_Flag Asserted during vertical no-display period every frame. Write 0 to clear it.
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Display 31 R/W 0 TCON1_En 0: disable 1: enable 30:9 / / / 8:4 R/W 0 Start_Delay This is for DE1 and DE2 3:2 / / / 1 R/W 0 TCON1_Src_Sel 00: DE 0 01: BLUE data(FIFO2 disable,RGB = 0000FF) 0 / / / Offset: 0x0094 ia l 7.2.7.5.
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Display width is TCON1_XO+1 15:12 / / / 11:0 R/W 0 TCON1_YO height is TCON1_YO+1 7.2.7.8. TCON1 Basic Timing Register3 (Default Value: 0x00000000) Offset: 0x00A0 Register Name: TCON1_BASIC3_REG R/W Default/Hex Description 31:29 / / / 28:16 R/W 0 HT horizontal total time Thcycle = (HT+1) * Thdclk 15:12 / / / 11:0 R/W 0 HBP horizontal back porch Thbp = (HBP +1) * Thdclk nt ia l Bit Offset: 0x00A4 id e 7.2.7.9.
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Display 9:0 R/W 0 VSPW vertical Sync Pulse Width (in lines) Tvspw = (VSPW+1) * Th Note: VT/2 > (VSPW+1) 7.2.7.11. TCON CEU Control Register (Default Value: 0x00000000) Offset: 0x0100 Register Name: TCON_CEU_CTL_REG R/W Default/Hex Description 31 R/W 0 CEU_en 0: bypass 1: enable 30:0 / / / ia l Bit Register Name: TCON_CEU_COEF_MUL_REG Bit R/W Default/Hex 31:13 / / 12:0 R/W 0 Description id e Offset: 0x0110+N*0x04 (N=0,1,2,4,5,6,8,9,10) nt 7.2.7.12.
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Display N=1: Gc N=2: Bc 7.2.7.14. TCON CEU Coefficient Rang Register (Default Value: 0x00000000) Offset: 0x0140+N*0x4 (N=0,1,2) Register Name: TCON_CEU_COEF_RANG_REG R/W Default/Hex Description 31:24 / / / 23:16 R/W 0 CEU_Coef _Range_Min unsigned 8bit value, range of [0,255] 15:8 / / / 7:0 R/W 0 CEU Coef _Range_Max unsigned 8bit value, range of [0,255] ia l Bit Register Name: TCON1_FILL_CTL_REG Bit R/W Default/Hex 31 R/W 0 30:0 / / Description id e Offset: 0x0300 nt 7.
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Display 7.2.7.18. TCON1 Fill Data Register (Default Value: 0x00000000) Register Name: TCON1_FILL_DATA_REG Bit R/W Default/Hex Description 31:24 / / / 23:0 R/W 0 Fill_Value co nf id e nt ia l Offset: 0x030C+N*0x0C(N=0,1,2) H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces Chapter 8 Interfaces This chapter describes the H3 interfaces, including: nf id e nt ia l TWI SPI UART CIR Receiver USB I2S/PCM OWA SCR EMAC TSC co           H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces 8.1. TWI 8.1.1. Overview This TWI Controller is designed to be used as an interface between CPU host and the serial TWI bus. It can support all the standard TWI transfer, including Slave and Master. The communication to the TWI bus is carried out on a byte-wise basis using interrupt or polled handshaking. This TWI Controller can be operated in standard mode (100K bps) or fast-mode, supporting data rate up to 400K bps.
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Interfaces SDA IIC1 IIC3 IIC4 IIC5 IIC2 SCL Figure 8-1. TWI Timing Diagram 8.1.3. TWI Controller Special Requirement Width Direction Description TWI_SCL 1 IN/OUT TWI Clock line TWI_SDA 1 IN/OUT TWI Serial Data line nt Port Name ia l 8.1.3.1. TWI Pin List id e 8.1.3.2. TWI Controller Operation nf There are four operation modes on the TWI bus which dictates the communications method. They are Master Transmit, Master Receive, Slave Transmit and Slave Receive.
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Interfaces 0x01C2AC00 TWI1 0x01C2B000 TWI2 0x01C2B400 Register Name Offset Description TWI_ADDR 0x0000 TWI Slave address TWI_XADDR 0x0004 TWI Extended slave address TWI_DATA 0x0008 TWI Data byte TWI_CNTR 0x000C TWI Control register TWI_STAT 0x0010 TWI Status register TWI_CCR 0x0014 TWI Clock control register TWI_SRST 0x0018 TWI Software reset TWI_EFR 0x001C TWI Enhance Feature register TWI_LCR 0x0020 TWI Line Control register TWI Controller Register Description nt 8.1.5.
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Interfaces does not generate an interrupt at this point.) If the next byte of the address matches the XADDR register (SLAX7 – SLAX0), the TWI generates an interrupt and goes into slave mode. 8.1.5.2. TWI Extend Address Register(Default Value: 0x00000000) Offset: 0x04 Register Name: TWI_XADDR Bit R/W Default/Hex Description 31:8 / / / R/W 0 8.1.5.3.
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Interfaces is set to ‘1’ when the TWI Controller is already in master mode and one or more bytes have been transmitted, then a repeated START condition will be sent. If the M_STA bit is set to ‘1’ when the TWI is being accessed in slave mode, the TWI will complete the data transfer in slave mode then enter master mode when the bus has been released. The M_STA bit is cleared automatically after a START condition has been sent: writing a ‘0’ to this bit has no effect.
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Interfaces 8.1.5.5.
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Interfaces 8.1.5.6.
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Interfaces 8.1.5.9.
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Interfaces 0: CPU has higher priority 1: DVFS has higher priority 1 R/W 0 CPU_BUSY_SET CPU Busy set 0 R/W 0 DVFC_BUSY_SET DVFS Busy set co nf id e nt ia l Notes:This register is only implemented in TWI0. H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces 8.2. SPI 8.2.1. Overview The SPI is the Serial Peripheral Interface which allows rapid data communication with fewer software interrupts. It can interface with up to four slave external devices or one single external master.The SPI module contains one 64x8 receiver buffer (RXFIFO) and one64x8 transmit buffer (TXFIFO). It can work at two modes: Master mode and Slave mode. SPI Timing Diagram nf 8.2.2.
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Interfaces SPI_SCLK (Mode 0) SPI_SCLK (Mode 2) SPI_MOSI SPI_MISO SPI_SS Sample MOSI/ MISO pin Phase 0 ia l Figure 8-2. SPI Phase 0 Timing Diagram SPI_SCLK (Mode 1) nt SPI_SCLK (Mode 3) SPI_MOSI id e SPI_MISO SPI_SS nf Sample MOSI/ MISO pin Phase 1 co Figure 8-3. SPI Phase 1 Timing Diagram 8.2.3. SPI Pin List The direction of SPI pin is different in two work modes: Master Mode and Slave Mode.
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Interfaces 0x01C68000 SPI1 0x01C69000 Register Name Offset Description SPI_GCR 0x04 SPI Global Control Register SPI_TCR 0x08 SPI Transfer Control register / 0x0c reserved SPI_IER 0x10 SPI Interrupt Control register SPI_ISR 0x14 SPI Interrupt Status register SPI_FCR 0x18 SPI FIFO Control register SPI_FSR 0x1C SPI FIFO Status register SPI_WCR 0x20 SPI Wait Clock Counter register SPI_CCR 0x24 SPI Clock Rate Control register / 0x28 reserved / 0x2c reserved SPI_MBC 0x30 S
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Interfaces SPI Function Mode Select 0: Slave Mode 1: Master Mode Note: Can’t be written when XCH=1 0 R/W EN SPI Module Enable Control 0: Disable 1: Enable 0 8.2.5.2. SPI Transfer Control Register(Default Value: 0x00000087) Offset: 0x08 R/W Default/Hex Description XCH Exchange Burst In master mode it is used to start SPI burst 0: Idle 1: Initiates exchange. Write “1” to this bit will start the SPI burst, and will auto clear after finishing the bursts transfer specified by BC.
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Interfaces 10 9 R/W R/W 0x0 0x0 DDB Dummy Burst Type 0: The bit value of dummy SPI burst is zero 1: The bit value of dummy SPI burst is one Note：Can’t be written when XCH=1. 0x0 DHB Discard Hash Burst In master mode it controls whether discarding unused SPI bursts 0: Receiving all SPI bursts in BC period 1: Discard unused SPI bursts, only fetching the SPI bursts during dummy burst period. The bursts number is specified by TC. Note：Can’t be written when XCH=1.
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Interfaces Note：Can’t be written when XCH=1. 2 1 R/W SPOL SPI Chip Select Signal Polarity Control 0: Active high polarity (0 = Idle) 1: Active low polarity (1 = Idle) Note：Can’t be written when XCH=1. 0x1 R/W CPOL SPI Clock Polarity Control 0: Active high polarity (0 = Idle) 1: Active low polarity (1 = Idle) 0x1 Note：Can’t be written when XCH=1.
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Interfaces RX FIFO Overflow Interrupt Enable 0: Disable 1: Enable 7 6 5 R R/W R/W 0x0 Reserved.
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Interfaces shifted out all the bits. Writing 1 to this bit clears it. 0: Busy 1: Transfer Completed 10 R/W R/W 0 0 TF_OVF TXFIFO Overflow This bit is set when if the TXFIFO is overflow. Writing 1 to this bit clears it. 0: TXFIFO is not overflow 1: TXFIFO is overflowed 0 RX_UDF RXFIFO Underrun When set, this bit indicates that RXFIFO has underrun. Writing 1 to this bit clears it. RX_OVF RXFIFO Overflow When set, this bit indicates that RXFIFO has overflowed. Writing 1 to this bit clears it.
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Interfaces 1: Full 1 0 R/W R/W 1 RX_EMP RXFIFO Empty This bit is set when the RXFIFO is empty . Writing 1 to this bit clears it. 0: Not empty 1: empty 0 RX_RDY RXFIFO Ready 0: RX_WL < RX_TRIG_LEVEL 1: RX_WL >= RX_TRIG_LEVEL This bit is set any time if RX_WL >= RX_TRIG_LEVEL. Writing “1” to this bit clears it. Where RX_WL is the water level of RXFIFO.
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Interfaces RX Test Mode Enable 0: Disable 1: Enable Note: In normal mode, RX FIFO can only be written by SPI controller, write ‘1’ to this bit will switch RX FIFO read and write function to AHB bus. This bit is used to test the RX FIFO, don’t set in normal operation and don’t set RF_TEST and TF_TEST at the same time.
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Interfaces These bits indicate the number of words in RX FIFO 0: 0 byte in RX FIFO 1: 1 byte in RX FIFO … 64:64 bytes in RX FIFO 8.2.5.7. SPI Wait Clock Register(Default Value: 0x00000000) Offset: 0x20 Register Name: SPI_WAIT Bit R/W Default/Hex Description 31:20 / / / 0x0 15:0 R/W 0 ia l R/W co nf id e nt 19:16 SWC Dual mode direction switch wait clock counter (for master mode only).
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Interfaces The SPI_SCLK is determined according to the following equation: SPI_CLK = Source_CLK / (2*(n + 1)). 8.2.5.9. SPI Master Burst Counter Register(Default Value: 0x00000000) Offset: 0x30 Register Name: SPI_BC R/W Default/Hex Description 31:24 / / / 0 MBC Master Burst Counter In master mode, this field specifies the total burst number. 0: 0 burst 1: 1 burst … N: N bursts R/W nt 23:0 ia l Bit 8.2.5.10.
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Interfaces Note：Can’t be written when XCH=1. 27:24 0x0 R/W STC Master Single Mode Transmit Counter In master mode, this field specifies the burst number that should be sent in single mode before automatically sending dummy burst. This is the first transmit counter in all bursts. 0: 0 burst 1: 1 burst … N: N bursts 0x0 nt ia l 23:0 R/W DBC Master Dummy Burst Counter In master mode, this field specifies the burst number that should be sent before receive in dual SPI mode.
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Interfaces co nf id e nt ia l This register can be accessed in byte, half-word or word unit by AHB. In byte accessing method, if there are data in RXFIFO, the top word is returned and the RXFIFO depth is decreased by 1. In half-word accessing method, two SPI bursts are returned and the RXFIFO depth is decrease by 2. In word accessing method, the four SPI bursts are returned and the RXFIFO depth is decreased by 4.
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Interfaces 8.3. UART 8.3.1. Overview The UART is used for serial communication with a peripheral, modem (data carrier equipment, DCE) or data set. Data is written from a master (CPU) over the APB bus to the UART and it is converted to serial form and transmitted to the destination device. Serial data is also received by the UART and stored for the master (CPU) to read back. ia l The UART contains registers to control the character length, baud rate, parity generation/checking, and interrupt generation.
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Interfaces Data Bits Bit Time SIN/SOUT S Stop 3/16 Bit Time 3/16 Bit Time SIR_OUT 3/16 Bit Time SIR_IN Figure 8-5. Serial IrDA Data Format 8.3.3.
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Interfaces 8.3.4. UART Controller Register List There are 5 UART controllers. All UART controllers can be configured as Serial IrDA.
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Interfaces If in FIFO mode and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an overrun error occurs. 8.3.5.2.
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Interfaces 8.3.5.4. UART Divisor Latch High Register(Default Value: 0x00000000) Offset: 0x0004 Register Name: UART_DLH R/W Default/Hex Description 31:8 / / / 0 DLH Divisor Latch High Upper 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero).
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Interfaces Enable Transmit Holding Register Empty Interrupt This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0: Disable 1: Enable 0 R/W ERBFI Enable Received Data Available Interrupt This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts.
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Interfaces Received available 1100 Second 0010 data Receiver data available (non-FIFO mode or FIFOs disabled) or RCVR FIFO trigger level reached (FIFO mode and FIFOs enabled) Reading the receiver buffer register (non-FIFO mode or FIFOs disabled) or the FIFO drops below the trigger level (FIFO mode and FIFOs enabled) Character timeout indication No characters in or out of the RCVR FIFO during the last 4 character times and there is at least 1character in it during This time Reading the receiver buff
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Interfaces TX Empty Trigger Writes have no effect when THRE_MODE_USER = Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. 00: FIFO empty 01: 2 characters in the FIFO 10: FIFO ¼ full 11: FIFO ½ full W 0 0 XFIFOR XMIT FIFO Reset This resets the control portion of the transmit FIFO and treats the FIFO as empty.
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Interfaces Break Control Bit This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE = Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed.
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Interfaces 8.3.5.9. UART Modem Control Register(Default Value: 0x00000000) Offset: 0x0010 Register Name: UART_MCR Bit R/W Default/Hex Description 31:6 / / / 0 AFCE Auto Flow Control Enable When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled. 0: Auto Flow Control Mode disabled 1: Auto Flow Control Mode enabled LOOP Loop Back Mode 0: Normal Mode 1: Loop Back Mode This is used to put the UART into a diagnostic mode for test purposes.
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Interfaces value written to this location is inverted and driven out on dtr_n. 0：dtr_n de-asserted (logic 1) 1：dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. 8.3.5.10.
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Interfaces 0 0 PE Parity Error This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]).
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Interfaces This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. 8.3.5.11. UART Modem Status Register(Default Value: 0x00000000) Offset: 0x0018 Register Name: UART_MSR R/W Default/Hex Description 31:8 / / / 0 DCD Line State of Data Carrier Detect This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n.
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Interfaces This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0: no change on dcd_n since last read of MSR 1: change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. Note: Ff the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted.
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Interfaces Scratch Register This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART. 8.3.5.13. UART Status Register(Default Value: 0x00000006) Offset: 0x007C Register Name: UART_USR R/W Default/Hex Description 31:5 / / / 0 RFF Receive FIFO Full This is used to indicate that the receive FIFO is completely full. 0: Receive FIFO not full 1: Receive FIFO Full This bit is cleared when the RX FIFO is no longer full.
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Interfaces 31:7 6:0 / R / / 0 TFL Transmit FIFO Level This is indicates the number of data entries in the transmit FIFO. 8.3.5.15. UART Receive FIFO Level Register(Default Value: 0x00000000) Offset: 0x0084 Register Name: UART_RFL R/W Default/Hex Description 31:7 / / / 0 RFL Receive FIFO Level This is indicates the number of data entries in the receive FIFO.
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Interfaces co nf id e nt ia l 0 : Halt TX disabled 1 : Halt TX enabled Note: If FIFOs are not enabled, the setting of the halt TX register has no effect on operation. H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces 8.4. CIR Receiver 8.4.1. Overview The CIR includes the following features:     Full physical layer implementation Support CIR for remote control 64x8 bits FIFO for data buffer Programmable FIFO thresholds id e nt ia l For saving CPU resource, CIR receiver is implemented in hardware. The CIR receiver samples the input signal on the programmable frequency and records these samples into RX FIFO when one CIR signal is found on the air.
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Interfaces 8.4.3. CIR Receiver Register Description 8.4.3.1. CIR Receiver Control Register(Default Value: 0x00000000) Offset: 0x0000 Register Name: CIR_CTL Bit R/W Default/Hex Description 31:9 / / / R/W 0 7:6 / / / R/W 0 3:2 / / /. 0 RXEN Receiver Block Enable 0: Disable 1: Enable R/W 0 id e GEN Global Enable A disable on this bit overrides any other block or channel enables and flushes all FIFOs.
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Interfaces Bit R/W Default/Hex Description 31:8 / / / 7:0 R 0 Receiver Byte FIFO 8.4.3.4. CIR Receiver Interrupt Control Register(Default Value: 0x00000000) Offset: 0x002C Register Name: CIR_RXINT Bit R/W Default/Hex Description 31:14 / / / 0 RAL RX FIFO Available Received Byte Level for interrupt and DMA request TRIGGER_LEVEL = RAL + 1 0 DRQ_EN RX FIFO DMA Enable 0: Disable 1: Enable When set to ‘1’, the Receiver FIFO DRQ is asserted if reaching RAL.
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Interfaces 1: 1 byte available data in RX FIFO 2: 2 byte available data in RX FIFO … 64: 64 byte available data in RX FIFO 7 R 0x0 STAT Status of CIR 0x0 – Idle 0x1 – busy 6:5 / / / R/W 0 3:2 / / / 0 RPE Receiver Packet End Flag 0: STO was not detected. In CIR mode, one CIR symbol is receiving or not detected. 1: STO field or packet abort symbol (7’b0000,000 and 8’b0000,0000 for MIR and FIR) is detected. In CIR mode, one CIR symbol is received. This bit is cleared by writing a ‘1’.
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Interfaces can be calculated by ((ATHR + 1)*(ATHC? Sample Clock: 128*Sample Clock)). R/W 0x18 0xa NTHR Noise Threshold for CIR When the duration of signal pulse (high or low level) is less than NTHR, the pulse is taken as noise and should be discarded by hardware. 0: all samples are recorded into RX FIFO 1: If the signal is only one sample duration, it is taken as noise and discarded. 2: If the signal is less than (<=) two sample duration, it is taken as noise and discarded.
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Interfaces 8.5. USB 8.5.1. USB OTG Controller 8.5.1.1. Overview ia l The USB OTG is a Dual-Role Device controller, which supports both device and host functions which can also be configured as a Host-only or Device-only controller, fully compliant with the USB 2.0 Specification. It can support high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps) transfers in Host mode. It can support high-speed (HS, 480-Mbps), and full-speed (FS, 12-Mbps) in Device mode.
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id e nt ia l Interfaces USB Host Controller co 8.5.2. nf Figure 8-6. USB OTG Controller Block Diagram 8.5.2.1. Overview USB Host Controller is fully compliant with the USB 2.0 specification, Enhanced Host Controller Interface (EHCI) Specification, Revision 1.0, and the Open Host Controller Interface (OHCI) Specification Release 1.0a. The controller supports high-speed, 480-Mbps transfers (40 times faster than USB 1.
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Interfaces  Supports the UTMI+ Level 3 interface . The 8-bit bidirectional data buses are used.  Supports only 1 USB Root Port shared between EHCI and OHCI. 8.5.2.2. Block Diagram co nf id e nt ia l Figure 8-7 shows the USB Host Controller system-level block diagram: Figure 8-7. USB Host Controller Block Diagram 8.5.2.3. USB Host Timing Diagram Please refer USB2.0 Specification, Enhanced Host Controller Interface (EHCI) Specification, Version 1.
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Interfaces Register Name Offset Description EHCI Capability Register E_CAPLENGTH 0x000 EHCI Capability register Length Register E_HCIVERSION 0x002 EHCI Host Interface Version Number Register E_HCSPARAMS 0x004 EHCI Host Control Structural Parameter Register E_HCCPARAMS 0x008 EHCI Host Control Capability Parameter Register E_HCSPPORTROUTE 0x00c EHCI Companion Port Route Description EHCI Operational Register 0x010 EHCI USB Command Register E_USBSTS 0x014 EHCI USB Status Register E_USBINT
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Interfaces 8.5.2.5. EHCI Register Description 8.5.2.5.1. EHCI Identification Register(Default Value: Implementation Dependent) Offset: 0x0000 Bit 7:0 Register Name: CAPLENGTH R/W R Default/Hex Description 0x10 CAPLENGTH The value in these bits indicates an offset to add to register base to find the beginning of the Operational Register Space. 8.5.2.5.2.
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Interfaces to system software. This field will always fix with ‘0’. Port Routing Rules This field indicates the method used by this implementation for how all ports are mapped to companion controllers. The value of this field has the following interpretation: Value Meaning 0 The first N_PCC ports are routed to the lowest numbered function companion host controller, the next N_PCC port are routed to the next lowest function companion controller, and so on.
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Interfaces structure for an entire frame. 0 R Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register.
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Interfaces 8.5.2.5.6. EHCI USB Command Register (Default Value: 0x00080000,0x00080B00 if Asynchronous Schedule Park Capability is a one) Offset: 0x0010 Bit 31:24 Register Name: USBCMD R/W / Default/Hex Description 0 Reserved These bits are reserved and should be set to zero. Interrupt Threshold Control The value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts.
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Interfaces R/W 0 0 Interrupt on Async Advance Doorbell This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. SoftWare must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS.
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Interfaces 01b 512 elements(2048byts) 10b 256 elements(1024bytes)For resource-constrained condition 11b reserved The default value is ‘00b’. R/W 0 Run/Stop When set to a 1, the Host Controller proceeds with execution of the schedule. When set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears this bit.
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Interfaces Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). 12 R / 1 HC Halted This bit is a zero whenever the Run/Stop bit is a one.
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Interfaces transition detected on a suspended port. This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port’s Port Owner bit. 0 R/WC R/WC 0 0 USB Interrupt(USBINT) The Host Controller sets this bit to a one on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.
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Interfaces 0 R/W USB Interrupt Enable When this bit is 1, and the USBINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit 0 8.5.2.5.9. EHCI Frame Index Register (Default Value: 0x00000000) Offset: 0x001C Bit 31:14 Register Name: FRINDEX R/W / Default/Hex Description 0 Reserved These bits are reserved and should be zero.
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Interfaces 8.5.2.5.11. EHCI Current Asynchronous List Address Register (Default Value: Undefined) Offset: 0x0028 Bit 31:5 4:0 Register Name: ASYNCLISTADDR R/W Default/Hex Description R/W Link Pointer (LP) This field contains the address of the next asynchronous queue head to be executed. These bits correspond to memory address signals [31:5], respectively. / Reserved These bits are reserved and their value has no effect on operation.
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Interfaces 31:22 21 20 / R/W R/W 0 Reserved These bits are reserved for future use and should return a value of zero when read. 0 Wake on Disconnect Enable(WKDSCNNT_E) Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power is zero. The default value in this field is ‘0’. 0 Wake on Connect Enable(WKCNNT_E) Writing this bit to a one enable the port to be sensitive to device connects as wake-up events.
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Interfaces signal lines. These bits are used for detection of low-speed USB devices prior to port reset and enable sequence. This read only field is valid only when the port enable bit is zero and the current connect status bit is set to a one. The encoding of the bits are: Bit[11:10] USB State Interpretation 00b SE0 Not Low-speed device, perform EHCI reset. 10b J-state Not Low-speed device, perform EHCI reset. 01b K-state Low-speed device, release ownership of port.
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Interfaces 11 Suspend ia l When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
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Interfaces The default value of this bit is ‘0’. R/WC 0 0 Port Enabled/Disabled 1=Enable, 0=Disable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition(disconnect event or other fault condition) or by host software.
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Interfaces 8.5.2.6.1. HcRevision Register(Default Value: 0x00000010) Offset: 0x400 Register Name: HcRevision Read/Write Bit HCD HC Default/Hex Description 31:8 / / 0x00 Reserved 0x10 Revision This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this HC. For example, a value of 0x11 corresponds to version 1.1. All of the HC implementations that are compliant with this specification will have a value of 0x10. 7:0 R R ia l 8.5.2.
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Interfaces 11b USBSuspend A transition to USBOperational from another state causes SOF generation to begin 1 ms later. HCD may determine whether HC has begun sending SOFs by reading the StartoFrame field of HcInterruptStatus. This field may be changed by HC only when in the USBSUSPEND state. HC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port. HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a hardware reset.
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Interfaces restoring this value. CBSR No. of Control EDs Over Bulk EDs Served 0 1:1 1 2:1 2 3:1 3 4:1 The default value is 0x0. 8.5.2.6.3. HcCommandStatus Register(Default Value: 0x00000000) Offset: 0x408 Register Name: HcCommandStatus Read/Write HCD HC Default/Hex Description 31:18 / / 0x0 Reserved SchedulingOverrunCount These bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b.
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Interfaces causing the Control list processing to continue. If no TD is found on the Control list, and if the HCD does not set ControlListFilled, then ControlListFilled will still be 0 when HC completes processing the Control list and Control list processing will stop. 0 R/W R/E HostControllerReset This bit is by HCD to initiate a software reset of HC.
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Interfaces This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be Incremented. 8.5.2.6.5.
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Interfaces Read/Write Bit HCD HC Default/Hex Description 31 R/W R 0x0 MasterInterruptEnable A written ‘0’ to this field is ignored by HC. A ‘1’ written to this field disables interrupt generation due events specified in the other bits of this register. This field is set after a hardware or software reset.
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Interfaces 8.5.2.6.8. HcPeriodCurrentED Register(Default Value: 0x00000000) Offset: 0x41c Register Name: HcPeriodCurrentED(PCED) Read/Write 31:4 R HC R/W R R Default/Hex Description 0x0 PCED[31:4] This is used by HC to point to the head of one of the Periodec list which will be processed in the current Frame. The content of this register is updated by HC after a periodic ED has been processed. HCD may read the content in determining which ED is currently being processed at the time of reading.
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Interfaces ControlListFilled of in HcCommandStatus. If set, it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does nothing. HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared. When set, HCD only reads the instantaneous value of this register. Initially, this is set to zero to indicate the end of the Control list. R 8.5.2.6.11.
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Interfaces Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the PCED, through bit 0 to bit 3 must be zero in this field. 8.5.2.6.13. HcDoneHead Register(Default Value: 0x00000000) Offset: 0x430 Register Name: HcDoneHead Read/Write R 8.5.2.6.14. R 0x0 HcDoneHead[3:0] Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary.
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Interfaces 8.5.2.6.15. HcFmRemaining Register(Default Value: 0x00000000) Offset: 0x438 Register Name: HcFmRemaining Read/Write Bit HCD HC Default/Hex Description R R/W 0x0 30:14 / / 0x0 Reserved 0x0 FramRemaining This counter is decremented at each bit time. When it reaches zero, it is reset by loading the FrameInterval value specified in HcFmInterval at the next bit time boundary.
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Interfaces HcFmRemaining reaches the value specified, processing of the periodic lists will have priority over Control/Bulk processing. HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress. 8.5.2.6.18.
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Interfaces 10 R R Device Type This bit specifies that the Root Hub is not a compound device. The Root Hub is not permitted to be a compound device. This field should always read/write 0. 0x0 PowerSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled. It is implementation-specific. This field is only valid if the NoPowerSwitching field is cleared. 9 R/W R 0 All ports are powered at the same time. 1 Each port is powered individually.
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Interfaces … Bit15 Ganged-power mask on Port #15. DeviceRemovable Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit0 Reserved Bit1 Device attached to Port #1. Bit2 Device attached to Port #2. … R/W 8.5.2.6.21. R Bit15 0x0 Device attached to Port #15.
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Interfaces Reserved 1 0x0 OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If per-port overcurrent protection is implemented this bit is always ‘0’ 0x0 (Read)LocalPowerStatus When read, this bit returns the LocalPowerStatus of the Root Hub. The Root Hub does not support the local power status feature; thus, this bit is always read as ‘0’.
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Interfaces This bit is set when hardware events cause the PortEnableStatus bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. 0 no change in PortEnableStatus 1 change in PortEnableStatus ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.
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Interfaces 0 port power is off 1 port power is on (write)SetPortPower The HCD writes a ‘1’ to set the PortPowerStatus bit. Writing a ‘0’ has no effect. Note: This bit is always reads ‘1b’ if power switching is not supported. 7:5 / / 0x0 Reserved (read)PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared.
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Interfaces (write)SetPortSuspend The HCD sets the PortSuspendStatus bit by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does not set PortSuspendStatus; instead it sets ConnectStatusChange. This informs the driver that it attempted to suspend a disconnected port. (read)PortEnableStatus This bit indicates whether the port is enabled or disabled.
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Interfaces / / / 17 R/W 0 HSIC Connect detect 1 in this field enable the hsic phy to detect device connect pulse on the bus. This field only valid when the bit 1 is set. 16 R/W 0 HSIC Connect Interrupt Enable Enable the HSIC connect interrupt. This field only valid when the bit 1 is set.
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Interfaces When the HSIC Connect Interrupt Enable is set, 1 in this bit will generate an interrupt to the system. This register is valid on HCI1. 15:0 / / / 8.5.2.8. USB Host Clock Requirement Description HCLK System clock (provided by AHB bus clock). This clock needs to be >30MHz. CLK60M Clock from PHY for HS SIE, is constant to be 60MHz. CLK48M Clock from PLL for FS/LS SIE, is constant to be 48MHz. co nf id e nt ia l Name H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.
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Interfaces 8.6. I2S/PCM 8.6.1. Overview The I2S/PCM Controller has been designed to transfer streaming audio-data between the system memory and the codec chip. The controller supports standard I2S format, Left-justified Mode format, Right-justified Mode format, PCM Mode format and TDM Mode format. 8.6.2. co nf id e nt ia l The I2S/PCM controller includes the following features:  Supports industry-standard AMBA Peripheral Bus (APB) and it is fully compliant with the AMBA Specification, Revision 2.
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Interfaces Audio_PLL 8.6.3. 24.576Mhz or 22.5792Mhz generated by AUDIO-PLL to produce 48KHz or 44.1KHz serial frequency Functionalities Description 8.6.3.1. Typical Applications The I2S/PCM provides a serial bus interface for stereo and multichannel audio data. This interface is most commonly used by consumer audio market, including compact disc, digital audio tape, digital sound processors, and digital TV-sound. ia l 8.6.3.2.
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Interfaces 1 / fs LRCK Left Channel Right Channel BCLK DOUT/DIN 8 slot [TDM-I2S mode] 0 2 DOUT/DIN 4 slot [TDM-I2S mode] 0 2 DOUT/DIN 2 slot [I2S mode] 0 m slot … n-1n-2 4 6 1 3 1 3 5 7 1 m=0~7 1 0 sample MSB LSB ia l Figure 8-9.
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Interfaces 1 / fs LRCK Left Channel Right Channel BCLK 0 8 slot [TDM-Right mode] 2 4 slot [TDM-Right mode] 4 6 0 2 2 slot [Right-Justified mode] 3 0 m 5 7 1 3 1 m=0~7 slot … n-1n-2 1 1 0 sample MSB LSB ia l Figure 8-11.
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Interfaces 8.6.5. Operation Modes The software operation of the I2S/PCM is divided into five steps: system setup, PCM/I2S initialization, the channel setup, DMA setup and Enable/Disable module. These five steps are described in detail in the following sections. 8.6.5.1. System setup and I2S/PCM initialization ia l The first step in the system setup is properly programming the GPIO. Because the I2S/PCM port is a multiplex pin. You can find the function in the pin multiplex specification.
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Interfaces 8.6.6.
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Interfaces 1: output 17 R/W 1 LRCK_OUT 0: input 1: output 16 R/W 0 LRCKR_OUT 0: input 1: output 15:12 / / / 11 R/W 0 / 10 R/W 0 / 9 R/W 0 / R/W 0 7 / / / 0 OUT Mute 0: normal transfer 1: force DOUT to output 0 0 MODE_SEL Mode Selection 0: PCM mode (offset 0: DSP_B; offset 1: DSP_A) 1: Left mode (offset 0: LJ mode; offset 1: I2S mode) 2: Right-Justified mode 3: Reserved R/W R/W 0 LOOP Loop back test 0: Normal mode 1: Loop back test When set ‘1’, connecting the SDO0 with
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Interfaces 8.6.7.2. I2S/PCM Format Register0 (Default Value: 0x00000033) Offset: 0x04 Bit 31 R/W R/W R/W Default/Hex Description 0 SDI_SYNC_SEL 0: SDI use LRCK 1: SDI use LRCKR 0 LRCK_WIDTH (only apply in PCM mode ) LRCK width 0: LRCK = 1 BCLK width (short frame) 1: LRCK = 2 BCLK width (long frame) 0 LRCKR_PERIOD It is used to program the number of BCLKs per channel of sample frame.
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Interfaces Sample Resolution 0: Reserved 1: 8-bit 2: 12-bit 3: 16-bit 4: 20-bit 5: 24-bit 6: 28-bit 7: 32-bit 0 0x3 SW Slot Width Select 0: Reserved 1: 8-bit 2: 12-bit 3: 16-bit 4: 20-bit 5: 24-bit 6: 28-bit 7: 32-bit ia l R/W R/W nf 2:0 id e nt 3 EDGE_TRANSFER 0: SDO drive data and SDI sample data at the different BCLK edge 1: SDO drive data and SDI sample data at the same BCLK edge BCLK_POLARITY = 0, use negative edge BCLK_POLARITY = 1, use positive edge Offset: 0x08 Bit R/W 31:8 / 7 6
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Interfaces 3:2 1:0 R/W R/W 0 RX_PDM PCM Data Mode 0: Linear PCM 1: reserved 2: 8-bits u-law 3: 8-bits A-law 0 TX_PDM PCM Data Mode 0: Linear PCM 1: reserved 2: 8-bits u-law 3: 8-bits A-law Offset: 0x0C ia l 8.6.7.4.
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Interfaces 1: FIFO Overrun Pending IRQ Write ‘1’ to clear this interrupt 0 R/W RXA_INT RX FIFO Data Available Pending Interrupt 0: No Pending IRQ 1: Data Available Pending IRQ when data in RX FIFO are more than RX trigger level Write ‘1’ to clear this interrupt or automatic clear if interrupt condition fails. 0 8.6.7.5. I2S/PCM RX FIFO Register(Default Value: 0x00000000) Offset: 0x10 R/W Default/Hex Description 0 RX_DATA RX Sample Host can get one sample by reading this register.
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Interfaces 3 R/W / / 0 TXIM TX FIFO Input Mode (Mode 0, 1) 0: Valid data at the MSB of TXFIFO register 1: Valid data at the LSB of TXFIFO register Example for 20-bits transmitted audio sample: Mode 0: FIFO_I[31:0] = {APB_WDATA[31:12], 12’h0} Mode 1: FIFO_I[31:0] = {APB_WDATA[19:0], 12’h0} 0 RXOM RX FIFO Output Mode (Mode 0, 1, 2, 3) 00: Expanding ‘0’ at LSB of DA_RXFIFO register. 01: Expanding received sample sign bit at MSB of DA_RXFIFO register.
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Interfaces 8.6.7.8. I2S/PCM DMA & Interrupt Control Register(Default Value: 0x00000000) Offset: 0x1C Register Name: I2S/PCM_INT Bit R/W Default/Hex Description 31:8 / / / 0 TX_DRQ TX FIFO Empty DRQ Enable 0: Disable 1: Enable 0 TXUI_EN TX FIFO Under run Interrupt Enable 0: Disable 1: Enable 0 TXOI_EN TX FIFO Overrun Interrupt Enable 0: Disable 1: Enable When set to ‘1’, an interrupt happens when writing new audio data if TX FIFO is full.
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Interfaces 8.6.7.9. I2S/PCM TX FIFO Register(Default Value: 0x00000000) Offset: 0x20 Bit Register Name: I2S/PCM_TXFIFO R/W 31:0 W Default/Hex Description 0 TX_DATA TX Sample Transmitting left, right channel sample data should be written this register one by one. The left channel sample data is first and then the right channel sample. 8.6.7.10.
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Interfaces 3: Divide by 4 4: Divide by 6 5: Divide by 8 6: Divide by 12 7: Divide by 16 8: Divide by 24 9: Divide by 32 10: Divide by 48 11: Divide by 64 12: Divide by 96 13: Divide by 128 14: Divide by 176 15: Divide by 192 ia l 8.6.7.11. I2S/PCM TX Counter Register(Default Value: 0x00000000) R/W Default/Hex Description TX_CNT TX Sample Counter The audio sample number of sending into TXFIFO. When one sample is put into TXFIFO by DMA or by host IO, the TX sample counter register increases by one.
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Interfaces Bit R/W Default/Hex Description 31:10 / / / 0 TX_SLOT_HIZ 0: normal mode for the last half cycle of BCLK in the slot 1: turn to hi-z state for the last half cycle of BCLK in the slot 9 R/W 8 R/W 0 TXn_STATE 0: transfer level 0 when not transferring slot 1: turn to hi-z state when not transferring slot 7 / / / R/W 0 3 / / / 0 TX_SLOT_NUM TX Channel/Slot Number which between CPU/DMA and FIFO 0: 1 channel or slot ...
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Interfaces 8.6.7.15.
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Interfaces … 7: 8th sample 3 / / / 2:0 R/W 0 TXn_CH0_MAP TXn Channel0 Mapping 0: 1st sample … 7: 8th sample 8.6.7.16.
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Interfaces R/W 0 RX_CH5_MAP RX Channel5 Mapping 0: 1st sample … 7: 8th sample 19 / / / 18:16 R/W 0 RX_CH4_MAP RX Channel4 Mapping 0: 1st sample … 7: 8th sample 15 / / / 14:12 R/W 0 RX_CH3_MAP RX Channel3 Mapping 0: 1st sample … 7: 8th sample 11 / / / 10:8 R/W 0 RX_CH2_MAP RX Channel2 Mapping 0: 1st sample … 7: 8th sample 7 / / 6:4 R/W 0 3 / 2:0 R/W id e nt ia l 22:20 / co nf RX_CH1_MAP TX Channel1 Mapping 0: 1st sample … 7: 8th sample / / 0 RX_CH0_MAP RX Chann
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Interfaces 8.7. OWA 8.7.1. Overview The OWA(One Wire Audio) provides a serial bus interface for audio data between system. This interface is widely used for consumer audio connect. nt Functional Description id e 8.7.2.
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Interfaces RX FIFO Clock Diveder Channel Status Registers Receiver Registers FSM & Control OWA_IN APB I/F Channel status & user data buffers ia l Clock Divider TX FIFO nt DMA & INT OWA_OUT Transmitter nf co 8.7.2.4. OWA Frame Format id e Figure 8-13. OWA Block Diagram Figure 8-14. Sub-Frame Format H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces id e nt ia l Figure 8-15. Frame/block format co 8.7.2.5. Operation Modes nf Figure 8-16. Biphase-Mark Encoding The software operation of the OWA is divided into five steps: system setup, OWA initialization, the channel setup, DMA setup and Enable/Disable module. These five setups are described in detail in the following sections. 8.7.2.5.1. System setup and OWA initialization The first step In the OWA initialization is properly programming the GPIO.
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Interfaces 8.7.2.5.3. Enable and disable the OWA To enable the function, you can enable TX/RX by write the OWA_TX_CFIG[31] and OWA_RX_CFIG[0]. After that, you must enable OWA by write the Globe Enable bit to 1 in the OWA_CTL.The disable process is write the Globe Enable to 0. 8.7.3.
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Interfaces 1 R/W 0 GEN Globe Enable A disable on this bit overrides any other block or channel enables and flushes all FIFOs. 0: Disable 1: Enable 0 R/W 0 RST Reset 0: Normal 1: Reset Self clear to 0 Offset: 0x04 ia l 8.7.4.2.
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Interfaces 1: Channel status A&B generated form TX_CHSTA 0 R/W 0 TXEN 0: disabled 1: enabled 8.7.4.3.
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Interfaces RX Parity Error Pending Interrupt 0: No pending IRQ 1: RX Parity Error Pending Interrupt Write “1” to clear this interrupt / / / 6 R/W 0 TXU_INT TX FIFO Under run Pending Interrupt 0: No pending IRQ 1: FIFO Under run Pending Interrupt Write “1” to clear this interrupt 5 R/W 0 TXO_INT TX FIFO Overrun Pending Interrupt 0: No Pending IRQ 1: FIFO Overrun Pending Interrupt Write “1” to clear this interrupt 4 R/W 1 TXE_INT TX FIFO Empty Pending Interrupt 0: No Pending IRQ 1: FIFO Empty Pe
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Interfaces 8.7.4.6.
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Interfaces 8.7.4.7.
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Interfaces 0: Disable 1: Enable R/W 0 TXOI_EN TX FIFO Overrun Interrupt Enable 0: Disable 1: Enable 4 R/W 0 TXEI_EN TX FIFO Empty Interrupt Enable 0: Disable 1: Enable 3 / / / 2 R/W 0 RX_DRQ RX FIFO Data Available DRQ Enable When set to “1”, RX FIFO DMA Request is asserted if Data is available in RX FIFO 0: Disable 1: Enable 1 R/W 0 RXOI_EN RX FIFO Overrun Interrupt Enable 0: Disable 1: Enable 0 R/W 0 id e nt ia l 5 nf RXAI_EN RX FIFO Data Available Interrupt Enable 0: Disable 1:
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Interfaces one. The TX Counter register can be set to any initial value at any time. After been updated by the initial value, the counter register should count on base of this value. 8.7.4.11. OWA RX Counter Register(Default Value: 0x00000000) Offset: 0x28 Register Name: OWA_RX_CNT R/W Default/Hex Description 31:0 R/W 0 RX_CNT RX Sample counter The audio sample number of writing into RX FIFO. When one sample is written by Codec, the RX sample counter register increases by one.
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Interfaces Category code Indicates the kind of equipment that generates the digital audio interface signal.
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Interfaces R/W 0 WL Sample word length For bit 0 = “0”: 000: not indicated 001: 16 bits 010: 18 bits 100: 19 bits 101: 20 bits 110: 17 bits 111: Reserved co nf id e nt 3:1 ia l Original sampling frequency 0000: not indicated 0001: 192kHz 0010: 12kHz 0011: 176.4kHz 0100: Reserved 0101: 96kHz 0110: 8kHz 0111: 88.2kHz 1000: 16kHz 1001: 24kHz 1010: 11.025kHz 1011: 22.05kHz 1100: 32kHz 1101: 48kHz 1110: Reserved 1111: 44.
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Interfaces R/W Default/Hex Description 31: 30 / / / 29:28 R/W CA Clock Accuracy 00: Level 2 01: Level 1 10: Level 3 11: not matched 27:24 R/W FREQ Sampling frequency 0000: 44.1kHz 0001: not indicated 0010: 48kHz 0011: 32kHz 0100: 22.05kHz 0101: Reserved 0110: 24kHz 0111: Reserved R/W 0 CN Channel Number 19:16 R/W 0 SN Source Number 15:8 R/W 0 7:6 R/W 0 5:3 R/W 2 R/W id e nt 23:20 1000: Reserved 1001: 768kHz 1010: 96kHz 1011: Reserved 1100:176.
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Interfaces 1: no copyright is asserted 1 R/W 0 TYPE Audio Data Type 0: Linear PCM Samples 1: For none-linear PCM audio such as AC3, DTS, MPEG audio 0 R/W 0 PRO Application type 0: Consumer Application 1: Professional Application 8.7.4.15.
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Interfaces 100: 19 bits 101: 20 bits 110: 17 bits 111: Reserved For bit 0 = “1”: 000: not indicated 001: 20 bits 010: 22 bits 100: 23 bits 101: 24 bits 110: 21 bits 111: Reserved 0 MWL Max Word length 0: Maximum audio sample word length is 20 bits 1: Maximum audio sample word length is 24 bits nf id e nt ia l R/W co 0 H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces 8.8. SCR 8.8.1. Overview The Smart Card Reader (SCR) is a communication controller that transmits data between the system and Smart Card. The controller can perform a complete smart card session, including card activation, card deactivation. Cold/warm reset, Answer to Reset (ATR) response reception, data transfers, etc. SCR includes the following features: Supports APB slave interface for easy integration with AMBA-based host systems Supports the ISO/IEC 7816-3:1997(E) and EMV2000 (4.
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Interfaces Smart Card Reader SCR_Vcc SCR_Clk SCR Clock Generator SCR Registers SCR Interface SCR_Rst SCR_IO SCR Controller APB SCR_Vppen TX FIFO SCR_Vpppp SCR_Det RX FIFO SCR Timing Diagram SCR Special Requirement 8.8.4.1. Clock Generator nf 8.8.4. id e Please refer ISO/IEC 7816 and EMV2000 Specification. nt 8.8.3. ia l Figure 8-17. SCR Block Diagram co The Clock Generator generates the Smart Card Clock signal and the Baud Clock Impulse signal, used in timing the Smart Card Reader.
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Interfaces clock. The BUAD rate is given by the following equation: BAUD  BAUD f s y s c lk 2 * ( B A U D D IV  1) -- Baud rate of the data stream between Smart Card and Reader. The duration of one bit, Elementary Time Unit (ETU), is defined in the ISO/IEC 7816-3 specification. During the first answer to reset response after the cold reset, the initial ETU must be equal to 372 Smart Card Clock Cycles.
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Interfaces SCR_CSR 0x000 Smart Card Reader Control and Status Register SCR_INTEN 0x004 Smart Card Reader Interrupt Enable Register 1 SCR_INTST 0x008 Smart Card Reader Interrupt Status Register 1 SCR_FCSR 0x00c Smart Card Reader FIFO Control and Status Register SCR_FCNT 0x010 Smart Card Reader RX and TX FIFO Counter Register SCR_RPT 0x014 Smart Card Reader RX and TX Repeat Register SCR_DIV 0x018 Smart Card Reader Clock and Baud Divisor Register SCR_LTIM 0x01c Smart Card Reader Line Tim
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Interfaces Clock Stop Polarity The value of the scclk output during the clock stop state. 18 17 R/W R/W 0 PECRXE Parity Error Character Receive Enable Enables storage of the characters received with wrong parity in RX FIFO. 0 MSBF MSB First When high, inverse bit ordering convention (msb to lsb) is used. R/W 0 15:12 / / / 11 R/W 0 DEACTDeactivation. Setting of this bit initializes the deactivation sequence. When the deactivation is finished, the DEACT bit is automatically cleared.
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Interfaces 23 22 21 20 19 18 R/W R/W R/W R/W R/W R/W 0 SCDEA Smart Card Deactivation Interrupt Enable. 0 SCACT Smart Card Activation Interrupt Enable. 0 SCINS Smart Card Inserted Interrupt Enable. 0 SCREM Smart Card Removed Interrupt Enable. 0 ATRDONE ATR Done Interrupt Enable. 0 ATRFAIL ATR Fail Interrupt Enable. R/W 0 16 R/W 0 CLKSTOPRUN Smart Card Clock Stop/Run Interrupt Enable. 15:13 / / / 12 R/W 0 RXPERR RX Parity Error Interrupt Enable. 0 RXDONE RX Done Interrupt Enable.
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Interfaces 22 21 20 19 R/W R/W R/W R/W R/W 0 0 SCACT Smart Card Activation Interrupt. When enabled, this interrupt is asserted after the Smart Card activation sequence is complete. 0 SCINS Smart Card Inserted Interrupt. When enabled, this interrupt is asserted after the smart card insertion. 0 SCREM Smart Card Removed Interrupt. When enabled, this interrupt is asserted after the smart card removal. 0 ATRDONE ATR Done Interrupt.
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Interfaces RX FIFO Full Interrupt. When enabled, this interrupt is asserted if the RX FIFO is filled up. / / / 7:5 / / / 0 TXPERR TX Parity Error Interrupt. When enabled, this interrupt is asserted if the Smart Card signals wrong character parity during the guard time after the character transmission was repeated TXREPEAT times or T=1 protocol is used. 0 TXDONE TX Done Interrupt. When enabled, this interrupt is asserted after one character was transmitted to the smart card.
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Interfaces 8.8.6.5. Smart Card Reader FIFO Counter Register(Default Value: 0x00000000) Offset: 0x10 31:24 23:16 15:8 R/W R/W R R Default/Hex Description 0 RXFTH RX FIFO Threshold These bits set the interrupt threshold of RX FIFO. The interrupt is asserted when the number of bytes it receives is equal to, or exceeds the threshold. 0 TXFTH TX FIFO Threshold These bits set the interrupt threshold of TX FIFO.
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Interfaces generate the Baud Clock impulses from the system clock. BAUD  f s y s c lk 2 * ( B A U D D IV  1) SCCDIV Smart Card Clock Divisor. This 16-bit register defines the divisor value used to generate the Smart Card Clock from the system clock. f s c c lk  f s c c lk R/W is the frequency of Smart Card Clock Signal. f s y s c lk 0 2 * ( S C C D IV  1) is the frequency of APB Clock. ia l 15:0 f s y s c lk Offset: 0x1C nt 8.8.6.8.
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Interfaces Bit R/W Default/Hex Description 31:16 R/W 0 CHARLIMIT Character Limit. This 16-bit register sets the maximum time between the leading edges of two consecutive characters. The value is ETUs. 15:8 / / / 0 GUARDTIME Character Guard time. This 8-bit register sets a delay at the end of each character transmitted from the Smart Card Reader to the Smart Card. The value is in ETUs. The parity error is besides signaled during the guard time. 7:0 R/W 8.8.6.10.
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Interfaces 8.8.6.11. Smart Card Reader FIFO Data Register(Default Value: 0x00000000) Offset: 0x0100 Register Name: SCR_FIFO Bit R/W Default/Hex Description 31:8 / / / 0 FIFO_DATA This 8-bit register provides access to the RX and TX FIFO buffers. The TX FIFO is accessed during the APB write transfer. The RX FIFO is accessed during the APB read transfer. R/W co nf id e nt ia l 7:0 H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces 8.9. EMAC 8.9.1. Overview The Ethernet MAC(EMAC) controller enables a host to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard. It supports 10M/100M/1000M external PHY with MII/ RGMII interface in both full and half duplex mode. The Ethernet MAC-DMA is designed for packet-oriented data transfers based on a linked list of descriptors. 4K Byte TXFIFO and 16K Byte RXFIFO are provided to keep continuous transmission and reception.
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Interfaces DMA TXFIFO RXFIFO TXFC RXFC MII EMAC RMII AHB Master PHY Interface MAC CSR DMA CSR OMR Register RGMII ia l AHB Slave 8.9.3. id e nt Figure 8-19.
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Interfaces 0x48 Management Interface Command Register MII_DATA 0x4C Management Interface Data Register ADDR_HIGH_0 0x50 MAC Address High Register 0 ADDR_LOW_0 0x54 MAC Address High Register 0 ADDR_HIGH_x 0x50+8*x MAC Address High Register x(x:1~7) ADDR_LOW_x 0x54+8*x MAC Address Low Register x(x:1~7) TX_DMA_STA 0xB0 Transmit DMA Status Register TX_CUR_DESC 0xB4 Current Transmit Descriptor Register TX_CUR_BUF 0xB8 Current Transmit Buffer Address Register RX_DMA_STA 0xC0 Receive DM
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Interfaces 29:24 R/W 8 BURST_LEN The burst length of RX and TX DMA transfer. 23:2 / / / 0 RX_TX_PRI 0: RX DMA and TX DMA have same priority 1: RX DMA has priority over TX DMA 0 SOFT_RST When this bit is set, soft reset all registers and logic. All clock inputs must be valid before soft rest. This bit is cleared internally when the reset operation is completed fully. Before write any register, this bit should read a 0. 1 R/W 0 R/W 8.9.4.3.
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Interfaces When this bit is asserted, the transmitter had been excessively active. 2 R 1 R 0 R 0 TX_BUF_UA_INT When this asserted, the TX DMA can not acquire next TX descriptor and TX DMA FSM is suspended. The ownership of next TX descriptor should be changed to TX DMA. The TX DMA FSM will resume when write to DMA_TX_START bit. 0 TX_DMA_STOPPED_INT When this bit is asserted, the TX DMA FSM is stopped. 0 TX_INT When this bit is asserted, a frame transmission is completed. 8.9.4.4.
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Interfaces 1: Enable transmit timeout interrupt 2 R/W 1 R/W 0 R/W 0 TX_BUF_UA_INT_EN 0: Disable transmit buffer available interrupt 1: Enable transmit buffer available interrupt 0 TX_DMA_STOPPED_INT_EN 0: Disable transmit DMA FSM stopped interrupt 1: Enable transmit DMA FSM stopped interrupt 0 TX_INT_EN 0: Disable transmit interrupt 1: Enable transmit interrupt 8.9.4.5. Transmit Control 0 Register(Default Value: 0x00000000) Description 0 TX_EN Enable transmitter.
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Interfaces 001: 128 010: 192 011: 256 Others: Reserved 7:2 1 / R/W 0 R/W / / 0 TX_MD 0: Transmission starts after the number of data in TX DAM FIFO is greater than TX_TH 1: Transmission starts after a full frame located in TX DMA FIFO 0 FLUSH_TX_FIFO The functionality that flush the data in the TX FIFO. 0: Enable 1: Disable ia l 8.9.4.7.
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Interfaces 8.9.4.8. Transmit DMA Descriptor List Address Register(Default Value: 0x00000000) Offset: 0x20 Bit 31:0 Register Name: TX_DMA_LIST R/W R/W Default/Hex Description 0 TX_DESC_LIST The base address of transmit descriptor list. It must be 32-bit aligned. 8.9.4.9.
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Interfaces 31 R/W 0 RX_DMA_START When set, the RX DMA will go no to work. It is cleared internally and always read a 0.
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Interfaces frame has been written to RX DMA FIFO 0 R/W FLUSH_RX_FRM The functionality that flush the frames when receive descriptors/buffers is unavailable 0: Enable 1: Disable 0 8.9.4.11. Receive DMA Descriptor List Address Register(Default Value: 0x00000000) Offset: 0x34 Bit R/W R/W Default/Hex Description 0 RX_DESC_LIST The base address of receive descriptor list. It must be 32-bit aligned.
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Interfaces 7 / 6 R/W 5 R/W / / 0 SA_FILTER_EN 0: Receive frames and update the result of SA filter 1: Update the result of SA filter. In addition, if the SA field of received frame does not match the values in SA MAC address registers, drop this frame.
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Interfaces 8.9.4.15. MII Command Register(Default Value: 0x00000000) Offset: 0x48 Register Name: MII_CMD Bit R/W Default/Hex Description 31:23 / / / MDC_DIV_RATIO_M MDC clock divide ration(m). The source of MDC clock is AHB clock. 000: 16 001: 32 010: 64 011: 128 22:20 R/W 0 Others: Reserved 19:17 / / / PHY_ADDR R/W 0 Select a PHY device from 32 possible candidates.
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Interfaces MAC_ADDR_0_HIGH 15:0 R/W 0xFFFF st The upper 16bits of the 1 MAC address. 8.9.4.18. MAC Address 0 Low Register(Default Value: 0xFFFFFFFF) Offset: 0x54 Bit Register Name: ADDR0_LOW R/W Default/Hex Description MAC_ADDR_0_LOW 31:0 R/W 0xFFFFFFFF st The lower 32bits of 1 MAC address. 8.9.4.19.
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Interfaces 8.9.4.21. Transmit DMA Status Register(Default Value: 0x00000000) Offset: 0xB0 Register Name: TX_DMA_STA Bit R/W Default/Hex Description 31:3 / / / TX_DMA_STA The state of Transmit DMA FSM. 000: STOP: When reset or disable TX DMA; 001: RUN_FETCH_DESC: Fetching TX DMA descriptor; 010: RUN_WAIT_STA: Waiting for the status of TX frame; 011: RUN_TRANS_DATA: Passing frame from host memory to TX DMA FIFO; 111: RUN_CLOSE_DESC: Closing TX descriptor.
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Interfaces 010, 110: Reserved. 8.9.4.25. Receive DMA Current Descriptor Register(Default Value: 0x00000000) Offset: 0xC4 Register Name: RX_DMA_CUR_DESC Bit R/W Default/Hex Description 31:0 R 0 The address of current receive descriptor 8.9.4.26. Receive DMA Current Buffer Address Register(Default Value: 0x00000000) Offset: 0xC8 Register Name: RX_DMA_CUR_BUF R/W Default/Hex Description 31:0 R 0 The address of current receive DMA buffer nt 8.9.4.27.
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Interfaces 1st Desc 2nd Desc 3rd Desc Desc List Base Addr N-th Desc … 1st: Status 1st: Status 1st: Status 1st: Status 2nd: Buffer Size 2nd: Buffer Size 2nd: Buffer Size 2nd: Buffer Size 2rd: Buffer Addr 2rd: Buffer Addr 2rd: Buffer Addr 2rd: Buffer Addr 4th: Next Desc 4th: Next Desc 4th: Next Desc 4th: Next Desc Figure 8-20. EMAC RX/TX Descriptor List ia l 8.9.5.1.
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Interfaces 0 TX_DEFER When set in Half-Duplex mode, the EMAC defers the frame transmission. 2nd Word of Transmit Descriptor Bits Description 31 TX_INT_CTL When set and the current frame have been transmitted, the TX_INT in Interrupt Status Register will be set. 30 LAST_DESC When set, current descriptor is the last one for current frame. 29 FIR_DESC When set, current descriptor is the first one for current frame. CHECKSUM_CTL These bits control to insert checksums in transmit frame.
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Interfaces 30 RX_DAF_FAIL When set, current frame don’t pass DA filter. 29:16 RX_FRM_LEN When LAST_DESC is not set and no error bit is set, this field is the length of received data for current frame. When LAST_DESC is set, RX_OVERFLOW_ERR and RX_NO_ENOUGH_BUF_ERR are not set, this field is the length of receive frame. 15 Reserved 14 RX_NO_ENOUGH_BUF_ERR When set, current frame is clipped because of no enough buffer. 13 RX_SAF_FAIL When set, current fame don’t pass SA filter. 12 Reserved.
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Interfaces 3rd Word of Receive Descriptor Bits Description 31:0 BUF_ADDR The address of buffer specified by current descriptor. 4th Word of Receive Descriptor Bits Description 31:0 NEXT_DESC_ADDR co nf id e nt ia l The address of next descriptor. This field must be 32-bit aligned. H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Interfaces 8.10. TSC 8.10.1. Overview The transport stream controller(TSC) is responsible for de-multiplexing and pre-processing the inputting multimedia data defined in ISO/IEC 13818-1. The transport stream controller receives multimedia data stream from SSI (Synchronous Serial Port)/SPI (Synchronous Parallel Port) inputs and de-multiplexing the data into Packets by PID (Packet Identify). Before the Packet to be store to memory by DMA, it can be pre-processing by the Transport Stream Descrambler.
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ia l Interfaces nt Figure 8-21. TSC Block Diagram nf id e Note: TSC – TS Controller TSF – TS Filter TSD – TS Descrambler TSG – TS Generator 8.10.2. Transport Stream Input Timing Diagram Name Clock Psync co Table 8-1. Input Signals Description Description Clock of SPI/SSI data input Packet sync (or Start flag) for TS packet Dvalid Data valid flag for TS data input Error Error flag for TS data, but do not used by TSC Data[7:0] TS data input.
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Interfaces nf id e nt ia l Figure 8-22. Input Timing for SPI mode (CLOCK = Rising Edge, PSYNC = High Active, DVALID = High Active, Packet Size = 188 Bytes) co Figure 8-23. Alternative Input Timing for SPI mode (CLOCK = Rising Edge, PSYNC = High Active, DVALID = High Active, Packet Size = 188 Bytes) Figure 8-24. Alternative Input Timing for SSI mode (CLOCK = Rising Edge, PSYNC = High Active, DVALID = High Active, Packet Size = 188 Bytes) H3 Datasheet(Revision1.
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Interfaces 8.10.3.
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Interfaces TSF_CBWPR TSF + 0x58 TSF Channel Buffer Write Pointer Register TSF_CBRPR TSF + 0x5c TSF Channel Buffer Read Pointer Register TSD_CTLR TSD + 0x00 TSD Control Register TSD_STAR TSD + 0x04 TSD Status Register TSD_CWIR TSD + 0x1c TSD Control Word Index Register TSD_CWR TSD + 0x20 TSD Control Word Register 8.10.4. Transport Stream Controller Register Description 8.10.4.1.
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Interfaces TS Input Port0 Parameters Definition 7:5 Reserved 4 SSI data order 0: MSB first for one byte data 1: LSB first for one byte data 3 CLOCK signal polarity 0 : Rise edge capturing 1: Fall edge capturing 2 ERROR signal polarity 0: High level active 1: Low level active 1 DVALID signal polarity 0: High level active 1: Low level active 0 PSYNC signal polarity 0: High level active 1: Low level active 8.10.4.5.
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Interfaces 31:26 / / / 25:24 R 0 TSGSts Status for TS Generator 0: IDLE state 1: Running state 2: PAUSE state Others: Reserved 23:10 / / / 0 TSGLBufMode Loop Buffer Mode When set to ‘1’, the TSG external buffer is in loop mode. 9 R/W R/W 0 7:3 / / / 0 TSGPauseBit Pause Bit for TS Generator Write ‘1’ to pause TS Generator. TS Generator would stop fetch new data from DRAM. After finishing this operation, this bit will clear to zero by hardware.
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Interfaces 15:8 / / / 7 R/W 0 SyncBytePos Sync Byte Position 0: the 1st byte position 1: the 5th byte position Notes: This bit is only used for 192 bytes packet size. 6:2 / / / 0 PktSize Packet Size Byte Size for one TS packet 0: 188 bytes Others: Reserved 8.10.4.9.
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Interfaces TS Generator (TSG) Half Finish Status Write ‘1’ to clear. 0 R/W TSGErrSyncByteSts TS Generator (TSG) Error Sync Byte Status Write ‘1’ to clear. 0 8.10.4.10. TSG Clock Control Register(Default Value: 0x00000000) Offset: TSG+0x0C Bit R/W R/W Default/Hex Description 0x0 TSGCDF_N TSG Clock Divide Factor (N) The Numerator part of TSG Clock Divisor Factor. 0x0 TSGCDF_D TSG Clock Divide Factor (D) The Denominator part of TSG Clock Divisor Factor.
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Interfaces 8.10.4.13. TSG Buffer Point Register(Default Value: 0x00000000) Offset: TSG+0x18 Register Name: TSG_BPR Bit R/W Default/Hex Description 31:24 / / / 0 TSGBufPtr Data Buffer Pointer for TS Generator Current TS generator data buffer read pointer (in byte unit) 23:0 R 8.10.4.14.
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Interfaces 2: By both PSYNC and Sync Byte 3: Reserved 7 R/W 0 SyncBytePos Sync Byte Position 0: the 1st byte position 1: the 5th byte position Notes: This bit is only used for 192 bytes packet size.
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Interfaces 1 0 R R 0 TSFCOIS TS PID Filter (TSF) Channel Overlap Status It is global status for 16 channel. It would clear to zero after all channels status bits are clear. 0 TSFCDIS TS PID Filter (TSF) Channel DMA status It is global status for 16 channel. It would clear to zero after all channels status bits are clear. 8.10.4.17.
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Interfaces Bit 31:0 R/W R/W Default/Hex Description 0x0 OLPIS Overlap Interrupt Status Overlap interrupt Status bits for channel 0~31. Set by hardware, and can be cleared by software writing ‘1’. When both these bits and the corresponding Overlap Interrupt Enable bits set, the TSF interrupt will generate. 8.10.4.21.
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Interfaces From Disable to Enable, internal status of the corresponding filter channel will be reset. 8.10.4.24. TSF PES Enable Register(Default Value: 0x00000000) Offset: TSF+0x34 Bit R/W R/W Default/Hex Description 0x0 PESEn PES Packet Enable for Channel 0~31 0: Disable 1: Enable These bits should not be changed during the corresponding channel enable.
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Interfaces Bit R/W Default/Hex Description 31:0 / / / 8.10.4.28. TSF Channel Status Register(Default Value: 0x00000000) Offset: TSF+0x44 Register Name: TSF_CSTAR Bit R/W Default/Hex Description 31:0 / / / 8.10.4.29. TSF Channel CW Index Register(Default Value: 0x00000000) Offset: TSF+0x48 Register Name: TSF_CCWIR R/W Default/Hex Description 31:3 / / / 0x0 CWIND Related Control Word Index Index to the control word used by this channel when Descramble Enable of this channel enable.
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Interfaces 8.10.4.32. TSF Channel Buffer Size Register(Default Value: 0x00000000) Offset: TSF+0x54 Register Name: TSF_CBSZR Bit R/W Default/Hex Description 31:26 / / / R/W 0 23:21 / / / 0 CHBufPktSz Data Buffer Packet Size for Channel The exact buffer size of buffer is N+1 bytes. The maximum buffer size is 2MB. This size should be 4-word (16Bytes) aligned. The LSB four bits should be zero.
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Interfaces This pointer should be changed by software after the data of buffer is read. 8.10.4.35. TSD Control Register(Default Value: 0x00000000) Offset: TSD+0x00 Register Name: TSD_CTLR R/W Default/Hex Description 31:2 / / / 0x0 DescArith Descramble Arithmetic 00: DVB CSA V1.1 Others: Reserved 8.10.4.36. R/W TSD Status Register(Default Value: 0x00000000) Offset: TSD+0x04 Register Name: TSD_STAR R/W Default/Hex Description 31:0 / / / id e Bit nt 1:0 ia l Bit 8.10.4.37.
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Interfaces R/W 0x0 co nf id e nt ia l 31:0 CWD Content of Control Word corresponding to the TSD_CWIR value H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.
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Electrical Characteristics Chapter 9 Electrical Characteristics 9.1. Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Table 9-1 specifies the absolute maximum ratings over the operating junction temperature range of commercial and extended temperature devices. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this standard may damage to the device.
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Electrical Characteristics 9.2. Recommended Operating Conditions All H3 modules are used under the operating Conditions contained in Table 9-2. Table 9-2. Recommended Operating Conditions Parameter Min Typ Max Unit Ta Ambient Operating Temperature -20 - +70 °C AVCC Power Supply for Analog part - 3.3 - V EPHY_VCC Power Supply for EPHY 2.8 3.3 3.6 V EPHY_VDD Power Supply for EPHY 1.0 1.1 1.2 V HVCC Power Supply for HDMI 3.0 3.3 3.6 V V33_TV Power Supply for TV 3.0 3.
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Electrical Characteristics 9.3. DC Electrical Characteristics Table 9-2 summarizes the DC electrical characteristics of H3. Table 9-3. DC Electrical Characteristics Parameter Min Typ Max Unit VIH High-Level Input Voltage 0.7*VCC_IO - VCC_IO+0.3 V VIL Low-Level Input Voltage -0.3 - 0.
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Electrical Characteristics 9.4. Oscillator Electrical Characteristics H3 contains two external input clocks:X24MIN and X32KIN, two output clocks:X24MOUT and X32KOUT.The 24.000MHz frequency is used to generate the main source clock for PLL and the main digital blocks，the clock is provided through X24MIN.Table 9-4 lists the 24MHz crystal specifications. Table 9-4. 24MHz Oscillator Characteristics Symbol Parameter Min Typ Max Unit 1/(tCPMAIN) Crystal Oscillator Frequency Range – 24.
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Electrical Characteristics 9.5. Power up and Power down Sequence The power rails for H3 is supported by discrete ICs. For the detailed information about discrete ICs, please see to their application notes.Figure 9-1 shows an example of the power-up sequence for H3 device, it contains 5V,3.3V,2.5V,1.8V,1.5V,1.25V,1.2V power rails. co nf id e nt ia l During the entire power-up sequence, the Reset pin must be held low until all power domains are stable.
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Electrical Characteristics VCC-IO (IC:AMS1117T33) T3 0.
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Appendix Appendix Pin Map The following figure shows the pin maps of the 347-pin FBGA package of H3 processor.
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Appendix Package Dimension co nf id en tia l The following diagram shows the package dimension of H3 processor,includes the top,bottom,side views and details of the 14mmx14mm package. H3 Datasheet(Revision 1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved.