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H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 100
0: Disable
1: Enable
When 25MHz crystal used, this PLL can output 24MHz.
17:16
R/W
0x0
PLL_24M_POST_DIV.
PLL 24M Output Clock Post Divider (When 25MHz crystal used).
1/2/3/4.
15:13
/
/
/
12:8
R/W
0x18
PLL_FACTOR_N.
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3
……
Factor=31, N=32
7:6
/
/
/
5:4
R/W
0x1
PLL_FACTOR_K.
PLL Factor K.(K=Factor + 1 )
The range is from 1 to 4.
3:2
/
/
/
1:0
R/W
0x1
PLL_FACTOR_M.
PLL Factor M (M = Factor + 1) is only valid in plltest debug.
The PLL_PERIPH back door clock output =24MHz*N*K/M.
The range is from 1 to 4.
4.3.5.9. PLL_DE Control Register (Default Value: 0x03006207)
Offset: 0x0048
Register Name: PLL_DE_CTRL_REG
Bit
R/W
Default/Hex
Description
31
R/W
0x0
PLL_ENABLE.
0: Disable
1: Enable
In the integer mode, The PLL Output= (24MHz*N)/M.
In the fractional mode, the PLL Output is select by bit 25.
Its default is 297MHz.
30:29
/
/
/
28
R
0x0
LOCK
0: Unlocked
1: Locked (It indicates that the PLL has been stable.)
27:26
/
/
/
25
R/W
0x1
FRAC_CLK_OUT.
PLL clock output when PLL_MODE_SEL=0(PLL_PREDIV_M factor must be set
to 0); no meaning when PLL_MODE_SEL =1.
0: PLL Output=270MHz
1: PLL Output =297MHz
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