Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 101
24
R/W
0x1
PLL_MODE_SEL.
0: Fractional Mode
1: Integer Mode
Note: When in Fractional mode, the Pre Divider M should be set to 0.
23:21
/
/
/
20
R/W
0x0
PLL_SDM_EN.
0: Disable
1: Enable
19:15
/
/
/
14:8
R/W
0x62
PLL_FACTOR_N
PLL Factor N.
Factor=0, N=1
Factor=1, N=2
Factor=2, N=3
……
Factor=0x7F, N=128
7:4
/
/
/
3:0
R/W
0x7
PLL_PRE_DIV_M.
PLL Per Divider (M = Factor+1).
The range is from 1 to 16.
4.3.5.10. CPUX/AXI Configuration Register (Default Value: 0x00010000)
Offset: 0x0050
Register Name: CPUX_AXI_CFG_REG
Bit
R/W
Default/Hex
Description
31:18
/
/
/
17:16
R/W
0x1
CPUX_CLK_SRC_SEL.
CPUX Clock Source Select.
CPUX Clock = Clock Source
00: LOSC
01: OSC24M
1X: PLL_CPUX
If the clock source is changed, at most to wait for 8 present running clock
cycles.
15:10
/
/
/
9:8
R/W
0x0
CPU_APB_CLK_DIV.
00: /1
01: /2
1x: /4
Note: System APB clock source is CPU clock source.
7:2
/
/
/
1:0
R/W
0x0
AXI_CLK_DIV_RATIO.
AXI Clock Divide Ratio.
AXI Clock source is CPU clock source.
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