Owners manual

System
H3 Datasheet(Revision1.2) Copyright© 2015 Allwinner Technology Co.,Ltd.All Rights Reserved. Page 102
00: /1
01: /2
10: /3
11: /4
4.3.5.11. AHB1/APB1 Configuration Register (Default Value: 0x00001010)
Offset: 0x0054
Register Name: AHB1_APB1_CFG_REG
Bit
R/W
Default/Hex
Description
31:14
/
/
/
13:12
R/W
0x1
AHB1_CLK_SRC_SEL.
00: LOSC
01: OSC24M
10: AXI
11: PLL_PERIPH0/ AHB1_PRE_DIV
11:10
/
/
/
9:8
R/W
0x0
APB1_CLK_RATIO.
APB1 Clock Divide Ratio. APB1 clock source is AHB1 clock.
00: /2
01: /2
10: /4
11: /8
7:6
R/W
0x0
AHB1_PRE_DIV
AHB1 Clock Pre Divide Ratio
00: /1
01: /2
10: /3
11: /4
5:4
R/W
0x1
AHB1_CLK_DIV_RATIO.
AHB1 Clock Divide Ratio.
00: /1
01: /2
10: /4
11: /8
3:0
/
/
/
4.3.5.12. APB2 Configuration Register (Default Value: 0x01000000)
Offset: 0x0058
Register Name: APB2_CFG_REG
Bit
R/W
Default/Hex
Description
31:26
/
/
/
25:24
R/W
0x1
APB2_CLK_SRC_SEL.
confidential